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From: <sv...@va...> - 2006-08-28 13:35:05
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Author: sewardj
Date: 2006-08-28 14:34:58 +0100 (Mon, 28 Aug 2006)
New Revision: 1651
Log:
Merge r1642 (x86/amd64 iropt e/rflag reduction rules)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c 2006-08-28 13:32:=
48 UTC (rev 1650)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c 2006-08-28 13:34:=
58 UTC (rev 1651)
@@ -958,12 +958,6 @@
binop(Iop_Shl64,cc_dep2,mkU8(32))));
}
=20
-//.. if (isU32(cc_op, AMD64G_CC_OP_SUBL) && isU32(cond, X86CondNZ)=
) {
-//.. /* long sub/cmp, then NZ --> test dst!=3Dsrc */
-//.. return unop(Iop_1Uto32,
-//.. binop(Iop_CmpNE32, cc_dep1, cc_dep2));
-//.. }
-
if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondL)) {
/* long sub/cmp, then L (signed less than)=20
--> test dst <s src */
@@ -992,12 +986,15 @@
binop(Iop_Shl64,cc_dep2,mkU8(32))));
}
=20
-//.. if (isU32(cc_op, AMD64G_CC_OP_SUBL) && isU32(cond, X86CondB))=
{
-//.. /* long sub/cmp, then B (unsigned less than)
-//.. --> test dst <u src */
-//.. return unop(Iop_1Uto32,
-//.. binop(Iop_CmpLT32U, cc_dep1, cc_dep2));
-//.. }
+ if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondNBE)) =
{
+ /* long sub/cmp, then NBE (unsigned greater than)
+ --> test src <u dst */
+ /* Note, args are opposite way round from the usual */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpLT64U,=20
+ binop(Iop_Shl64,cc_dep2,mkU8(32)),
+ binop(Iop_Shl64,cc_dep1,mkU8(32))));
+ }
=20
/*---------------- SUBW ----------------*/
=20
@@ -1029,6 +1026,14 @@
unop(Iop_64to8,cc_dep2)));
}
=20
+ if (isU64(cc_op, AMD64G_CC_OP_SUBB) && isU64(cond, AMD64CondNZ)) {
+ /* byte sub/cmp, then NZ --> test dst!=3Dsrc */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpNE8,=20
+ unop(Iop_64to8,cc_dep1),
+ unop(Iop_64to8,cc_dep2)));
+ }
+
if (isU64(cc_op, AMD64G_CC_OP_SUBB) && isU64(cond, AMD64CondS)
&& isU64(cc_dep2, 0)) {
/* byte sub/cmp of zero, then S --> test (dst-0 <s 0)
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2006-08-28 13:32:48=
UTC (rev 1650)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2006-08-28 13:34:58=
UTC (rev 1651)
@@ -1056,6 +1056,16 @@
return unop(Iop_1Uto32,binop(Iop_CmpLT32S, cc_dep1, mkU32(0)));
}
=20
+ /*---------------- DECW ----------------*/
+
+ if (isU32(cc_op, X86G_CC_OP_DECW) && isU32(cond, X86CondZ)) {
+ /* dec W, then Z --> test dst =3D=3D 0 */
+ return unop(Iop_1Uto32,
+ binop(Iop_CmpEQ32,=20
+ binop(Iop_Shl32,cc_dep1,mkU8(16)),=20
+ mkU32(0)));
+ }
+
/*---------------- INCW ----------------*/
=20
if (isU32(cc_op, X86G_CC_OP_INCW) && isU32(cond, X86CondZ)) {
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