[Valgrind-developers] Omega - found my problem...

[Bryan M. <om...@br...>]

Chaps,

finally got some time to work on Omega again and found what stops it 
from working with optimised code (debug code is fine for some reason):

Index: priv/guest-x86/toIR.c
===================================================================
--- priv/guest-x86/toIR.c       (revision 1574)
+++ priv/guest-x86/toIR.c       (working copy)
@@ -11330,8 +11330,8 @@
        t1 = newTemp(szToITy(sz)); t2 = newTemp(Ity_I32);
        assign(t2, getIReg(4, R_ESP));
        assign(t1, loadLE(szToITy(sz),mkexpr(t2)));
+      putIReg(sz, opc-0x58, mkexpr(t1));
        putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t2), mkU32(sz)));
-      putIReg(sz, opc-0x58, mkexpr(t1));
        DIP("pop%c %s\n", nameISize(sz), nameIReg(sz,opc-0x58));
        break;

That little patch reverses the order of assignments to sim cpu registers 
so that when you do a pop this happens:

ESP -> temp2
popped value -> temp1
temp1 -> sim cpu register
(calc new stack value from temp 2) -> ESP

instead of:

ESP -> temp2
popped value -> temp1
(calc new stack value from temp 2) -> ESP
temp1 -> sim cpu register


Is this an acceptable change? Is there another way of doing this? Does 
this break anyone else?

The reason I need this for omega is that the value is read from the 
stack but the stack content is invalidated (causing the "last pointer" 
that was on the stack to die, generating a false leak report) before the 
"last pointer" becomes visible in a client register. This way around, 
the "last pointer" gets a new reference (a client register) before the 
old one on the stack dies.

I would also need this for the other architectures but only have x86 to 
play on at home and won't be at work until Monday.

Comments welcome!

Bryan "Brain Murders" Meredith