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From: <sv...@va...> - 2006-01-26 03:03:18
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Author: sewardj
Date: 2006-01-26 03:02:26 +0000 (Thu, 26 Jan 2006)
New Revision: 1552
Log:
In 32-bit mode, handle F64toI64 and I64toF64.
Modified:
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-26 02:24:17 UTC (rev 1551)
+++ trunk/priv/host-ppc/isel.c 2006-01-26 03:02:26 UTC (rev 1552)
@@ -2478,6 +2478,35 @@
*rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
return;
=20
+ /* F64toI64 */
+ case Iop_F64toI64: {
+ HReg tLo =3D newVRegI(env);
+ HReg tHi =3D newVRegI(env);
+ HReg r1 =3D StackFramePtr(env->mode64);
+ PPCAMode* zero_r1 =3D PPCAMode_IR( 0, r1 );
+ PPCAMode* four_r1 =3D PPCAMode_IR( 4, r1 );
+ HReg fsrc =3D iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg ftmp =3D newVRegF(env);
+
+ vassert(!env->mode64);
+ /* Set host rounding mode */
+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+
+ sub_from_sp( env, 16 );
+ addInstr(env, PPCInstr_FpCftI(False/*F->I*/, False/*int64*/,
+ ftmp, fsrc));
+ addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_=
r1));
+ addInstr(env, PPCInstr_Load(4, tHi, zero_r1, False/*mode32*/=
));
+ addInstr(env, PPCInstr_Load(4, tLo, four_r1, False/*mode32*/=
));
+ add_to_sp( env, 16 );
+
+ /* Restore default FPU rounding. */
+ set_FPU_rounding_default( env );
+ *rHi =3D tHi;
+ *rLo =3D tLo;
+ return;
+ }
+
default:=20
break;
}
@@ -2814,6 +2843,32 @@
/* Restore default FPU rounding. */
set_FPU_rounding_default( env );
return fdst;
+ } else {
+ /* 32-bit mode */
+ HReg fdst =3D newVRegF(env);
+ HReg isrcHi, isrcLo;
+ HReg r1 =3D StackFramePtr(env->mode64);
+ PPCAMode* zero_r1 =3D PPCAMode_IR( 0, r1 );
+ PPCAMode* four_r1 =3D PPCAMode_IR( 4, r1 );
+
+ iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2);
+
+ /* Set host rounding mode */
+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+
+ sub_from_sp( env, 16 );
+
+ addInstr(env, PPCInstr_Store(4, zero_r1, isrcHi, False/*mode=
32*/));
+ addInstr(env, PPCInstr_Store(4, four_r1, isrcLo, False/*mode=
32*/));
+ addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1=
));
+ addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,=20
+ fdst, fdst));
+
+ add_to_sp( env, 16 );
+
+ /* Restore default FPU rounding. */
+ set_FPU_rounding_default( env );
+ return fdst;
}
}
}
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