|
From: <sv...@va...> - 2006-01-26 02:24:22
|
Author: sewardj
Date: 2006-01-26 02:24:17 +0000 (Thu, 26 Jan 2006)
New Revision: 1551
Log:
A bit more backend tidying:
- fix up more float-integer conversions
- remove unused signedness field on PPCInstr_Load
Modified:
trunk/priv/host-ppc/hdefs.c
trunk/priv/host-ppc/hdefs.h
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.c 2006-01-25 21:29:48 UTC (rev 1550)
+++ trunk/priv/host-ppc/hdefs.c 2006-01-26 02:24:17 UTC (rev 1551)
@@ -582,6 +582,7 @@
case Pun_NEG: return "neg";
case Pun_CLZ32: return "cntlzw";
case Pun_CLZ64: return "cntlzd";
+ case Pun_EXTSW: return "extsw";
default: vpanic("showPPCUnaryOp");
}
}
@@ -837,12 +838,11 @@
vassert(cond.test !=3D Pct_ALWAYS);
return i;
}
-PPCInstr* PPCInstr_Load ( UChar sz, Bool syned,
+PPCInstr* PPCInstr_Load ( UChar sz,
HReg dst, PPCAMode* src, Bool mode64 ) {
PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
i->tag =3D Pin_Load;
i->Pin.Load.sz =3D sz;
- i->Pin.Load.syned =3D syned;
i->Pin.Load.src =3D src;
i->Pin.Load.dst =3D dst;
vassert(sz =3D=3D 1 || sz =3D=3D 2 || sz =3D=3D 4 || sz =3D=3D 8);
@@ -1333,8 +1333,7 @@
Bool idxd =3D toBool(i->Pin.Load.src->tag =3D=3D Pam_RR);
UChar sz =3D i->Pin.Load.sz;
UChar c_sz =3D sz=3D=3D1 ? 'b' : sz=3D=3D2 ? 'h' : sz=3D=3D4 ? 'w'=
: 'd';
- HChar* s_syned =3D i->Pin.Load.syned ? "a" : sz=3D=3D8 ? "" : "z";
- vex_printf("l%c%s%s ", c_sz, s_syned, idxd ? "x" : "" );
+ vex_printf("l%cz%s ", c_sz, idxd ? "x" : "" );
ppHRegPPC(i->Pin.Load.dst);
vex_printf(",");
ppPPCAMode(i->Pin.Load.src);
@@ -2138,10 +2137,10 @@
switch (hregClass(rreg)) {
case HRcInt64:
vassert(mode64);
- return PPCInstr_Load( 8, False, rreg, am, mode64 );
+ return PPCInstr_Load( 8, rreg, am, mode64 );
case HRcInt32:
vassert(!mode64);
- return PPCInstr_Load( 4, False, rreg, am, mode64 );
+ return PPCInstr_Load( 4, rreg, am, mode64 );
case HRcFlt64:
return PPCInstr_FpLdSt ( True/*load*/, 8, rreg, am );
case HRcVec128:
@@ -2534,7 +2533,9 @@
UChar* ptmp =3D p;
vassert(nbuf >=3D 32);
=20
-// vex_printf("asm ");ppPPCInstr(i, mode64); vex_printf("\n");
+ if (0) {
+ vex_printf("asm ");ppPPCInstr(i, mode64); vex_printf("\n");
+ }
=20
switch (i->tag) {
=20
@@ -2797,8 +2798,13 @@
p =3D mkFormX(p, 31, r_src, r_dst, 0, 26, 0);
break;
case Pun_CLZ64: // cntlzd r_dst, r_src
+ vassert(mode64);
p =3D mkFormX(p, 31, r_src, r_dst, 0, 58, 0);
break;
+ case Pun_EXTSW: // extsw r_dst, r_src
+ vassert(mode64);
+ p =3D mkFormX(p, 31, r_src, r_dst, 0, 986, 0);
+ break;
default: goto bad;
}
goto done;
@@ -3011,28 +3017,25 @@
case Pin_Load: {
PPCAMode* am_addr =3D i->Pin.Load.src;
UInt r_dst =3D iregNo(i->Pin.Load.dst, mode64);
- Bool syned =3D i->Pin.Load.syned;
UInt opc1, opc2, sz =3D i->Pin.Load.sz;
switch (am_addr->tag) {
case Pam_IR:
switch(sz) {
- case 1: opc1 =3D 34; break;
- case 2: opc1 =3D (syned) ? 42: 40; break;
- case 4: opc1 =3D 32; break;
- case 8: opc1 =3D 58; break;
- default:
- goto bad;
+ case 1: opc1 =3D 34; break;
+ case 2: opc1 =3D 40; break;
+ case 4: opc1 =3D 32; break;
+ case 8: opc1 =3D 58; vassert(mode64); break;
+ default: goto bad;
}
p =3D doAMode_IR(p, opc1, r_dst, am_addr, mode64);
goto done;
case Pam_RR:
switch(sz) {
- case 1: opc2 =3D 87; break;
- case 2: opc2 =3D (syned) ? 343: 279; break;
- case 4: opc2 =3D 23; break;
- case 8: opc2 =3D 21; break;
- default:
- goto bad;
+ case 1: opc2 =3D 87; break;
+ case 2: opc2 =3D 279; break;
+ case 4: opc2 =3D 23; break;
+ case 8: opc2 =3D 21; vassert(mode64); break;
+ default: goto bad;
}
p =3D doAMode_RR(p, 31, opc2, r_dst, am_addr, mode64);
goto done;
@@ -3215,68 +3218,19 @@
p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 14, 0);
goto done;
}
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
False) {
+ // fctid (conv f64 to i64), PPC64 p437
+ p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 814, 0);
+ goto done;
+ }
+ if (i->Pin.FpCftI.fromI =3D=3D True && i->Pin.FpCftI.int32 =3D=3D =
False) {
+ // fcfid (conv i64 to f64), PPC64 p434
+ p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 846, 0);
+ goto done;
+ }
goto bad;
}
=20
-// case Pin_FpF64toI32: {
-// UInt r_dst =3D iregNo(i->Pin.FpF64toI32.dst, mode64);
-// UInt fr_src =3D fregNo(i->Pin.FpF64toI32.src);
-// UChar fr_tmp =3D 7; // Temp freg
-// PPCAMode* am_addr;
-//
-// // fctiw (conv f64 to i32), PPC32 p404
-// p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 14, 0);
-//
-// // No RI form of stfiwx, so need PPCAMode_RR:
-// am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
-// hregPPC_GPR0(mode64) );
-//
-// // stfiwx (store fp64[lo32] as int32), PPC32 p517
-// p =3D doAMode_RR(p, 31, 983, fr_tmp, am_addr, mode64);
-//
-// // lwzx (load int32), PPC32 p463
-// p =3D doAMode_RR(p, 31, 23, r_dst, am_addr, mode64);
-// goto done;
-// }
-//
-// case Pin_FpF64toI64: {
-// UInt r_dst =3D iregNo(i->Pin.FpF64toI64.dst, mode64);
-// UInt fr_src =3D fregNo(i->Pin.FpF64toI64.src);
-// UChar fr_tmp =3D 7; // Temp freg
-// PPCAMode* am_addr;
-//
-// // fctid (conv f64 to i64), PPC64 p437
-// p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 814, 0);
-//
-// am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
-// hregPPC_GPR0(mode64) );
-//
-// // stfdx (store fp64), PPC64 p589
-// p =3D doAMode_RR(p, 31, 727, fr_tmp, am_addr, mode64);
-//
-// // ldx (load int64), PPC64 p476
-// p =3D doAMode_RR(p, 31, 21, r_dst, am_addr, mode64);
-// goto done;
-// }
-//
-// case Pin_FpI64toF64: {
-// UInt r_src =3D iregNo(i->Pin.FpI64toF64.src, mode64);
-// UInt fr_dst =3D fregNo(i->Pin.FpI64toF64.dst);
-// UChar fr_tmp =3D 7; // Temp freg
-// PPCAMode* am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
-// hregPPC_GPR0(mode64) );
-//
-// // stdx r_src,r0,r1
-// p =3D doAMode_RR(p, 31, 149, r_src, am_addr, mode64);
-//
-// // lfdx fr7,r0,r1
-// p =3D doAMode_RR(p, 31, 599, fr_tmp, am_addr, mode64);
-//
-// // fcfid (conv i64 to f64), PPC64 p434
-// p =3D mkFormX(p, 63, fr_dst, 0, fr_tmp, 846, 0);
-// goto done;
-// }
-
case Pin_FpCMov: {
UInt fr_dst =3D fregNo(i->Pin.FpCMov.dst);
UInt fr_src =3D fregNo(i->Pin.FpCMov.src);
Modified: trunk/priv/host-ppc/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.h 2006-01-25 21:29:48 UTC (rev 1550)
+++ trunk/priv/host-ppc/hdefs.h 2006-01-26 02:24:17 UTC (rev 1551)
@@ -327,7 +327,8 @@
Pun_NEG,
Pun_NOT,
Pun_CLZ32,
- Pun_CLZ64
+ Pun_CLZ64,
+ Pun_EXTSW
}
PPCUnaryOp;
=20
@@ -450,7 +451,7 @@
Pin_Call, /* call to address in register */
Pin_Goto, /* conditional/unconditional jmp to dst */
Pin_CMov, /* conditional move */
- Pin_Load, /* load a 8|16|32|64 bit value from mem */
+ Pin_Load, /* zero-extending load a 8|16|32|64 bit value from=
mem */
Pin_Store, /* store a 8|16|32|64 bit value to mem */
Pin_Set, /* convert condition code to value 0 or 1 */
Pin_MfCR, /* move from condition register to GPR */
@@ -543,7 +544,7 @@
HReg srcL;
PPCRH* srcR;
} Cmp;
- /* Not and Neg */
+ /* Not, Neg, Clz32/64, Extsw */
struct {
PPCUnaryOp op;
HReg dst;
@@ -589,10 +590,9 @@
HReg dst;
PPCRI* src;
} CMov;
- /* Sign/Zero extending loads. Dst size is host word size */
+ /* Zero extending loads. Dst size is host word size */
struct {
UChar sz; /* 1|2|4|8 */
- Bool syned;
HReg dst;
PPCAMode* src;
} Load;
@@ -774,7 +774,7 @@
extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt );
extern PPCInstr* PPCInstr_Goto ( IRJumpKind, PPCCondCode cond, PPC=
RI* dst );
extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src=
);
-extern PPCInstr* PPCInstr_Load ( UChar sz, Bool syned,
+extern PPCInstr* PPCInstr_Load ( UChar sz,
HReg dst, PPCAMode* src, Bool mod=
e64 );
extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst,
HReg src, Bool mode64 );
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-25 21:29:48 UTC (rev 1550)
+++ trunk/priv/host-ppc/isel.c 2006-01-26 02:24:17 UTC (rev 1551)
@@ -1029,7 +1029,7 @@
if (e->Iex.Load.end !=3D Iend_BE)
goto irreducible;
addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),=20
- False, r_dst, am_addr, mode64 ));
+ r_dst, am_addr, mode64 ));
return r_dst;
break;
}
@@ -1305,7 +1305,7 @@
HReg fsrc =3D iselDblExpr(env, e->Iex.Binop.arg2);
HReg ftmp =3D newVRegF(env);
HReg idst =3D newVRegI(env);
- vassert(!env->mode64); // wait for 64-bit test case
+
/* Set host rounding mode */
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
@@ -1313,8 +1313,12 @@
addInstr(env, PPCInstr_FpCftI(False/*F->I*/, True/*int32*/,=20
ftmp, fsrc));
addInstr(env, PPCInstr_FpSTFIW(r1, ftmp));
- addInstr(env, PPCInstr_Load(4, True/*signed*/,=20
- idst, zero_r1, mode64));
+ addInstr(env, PPCInstr_Load(4, idst, zero_r1, mode64));
+
+ /* in 64-bit mode we need to sign-widen idst. */
+ if (mode64)
+ addInstr(env, PPCInstr_Unary(Pun_EXTSW, idst, idst));
+
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
@@ -1323,19 +1327,27 @@
}
=20
if (e->Iex.Binop.op =3D=3D Iop_F64toI64) {
- HReg fr_src =3D iselDblExpr(env, e->Iex.Binop.arg2);
- HReg r_dst =3D newVRegI(env); =20
- /* Set host rounding mode */
- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+ if (mode64) {
+ HReg r1 =3D StackFramePtr(env->mode64);
+ PPCAMode* zero_r1 =3D PPCAMode_IR( 0, r1 );
+ HReg fsrc =3D iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg idst =3D newVRegI(env); =20
+ HReg ftmp =3D newVRegF(env);
=20
- sub_from_sp( env, 16 );
-vassert(0);
-// addInstr(env, PPCInstr_FpF64toI64(r_dst, fr_src));
- add_to_sp( env, 16 );
+ /* Set host rounding mode */
+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
- /* Restore default FPU rounding. */
- set_FPU_rounding_default( env );
- return r_dst;
+ sub_from_sp( env, 16 );
+ addInstr(env, PPCInstr_FpCftI(False/*F->I*/, False/*int64*/,
+ ftmp, fsrc));
+ addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_=
r1));
+ addInstr(env, PPCInstr_Load(8, idst, zero_r1, True/*mode64*/=
));
+ add_to_sp( env, 16 );
+
+ /* Restore default FPU rounding. */
+ set_FPU_rounding_default( env );
+ return idst;
+ }
}
=20
break;
@@ -1366,7 +1378,7 @@
if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) {
HReg r_dst =3D newVRegI(env);
PPCAMode* amode =3D iselWordExpr_AMode( env, mi.bindee[0] );
- addInstr(env, PPCInstr_Load(2,False,r_dst,amode, mode64));
+ addInstr(env, PPCInstr_Load(2,r_dst,amode, mode64));
return r_dst;
}
}
@@ -1566,7 +1578,7 @@
addInstr(env,
PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 ));
addInstr(env,
- PPCInstr_Load( 4, False, dst, am_off12, mode64 ));
+ PPCInstr_Load( 4, dst, am_off12, mode64 ));
=20
add_to_sp( env, 32 ); // Reset SP
return dst;
@@ -1591,7 +1603,7 @@
PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 )=
);
addInstr(env,
PPCInstr_Load(=20
- 8, False, dst,=20
+ 8, dst,=20
op_unop =3D=3D Iop_V128HIto64 ? am_off0 : am_off=
8,=20
mode64 ));
=20
@@ -1624,8 +1636,7 @@
addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
fr_src, am_addr ));
// load as Ity_I64
- addInstr(env, PPCInstr_Load( 8, False,
- r_dst, am_addr, mode64 ));
+ addInstr(env, PPCInstr_Load( 8, r_dst, am_addr, mode64 ));
=20
add_to_sp( env, 16 ); // Reset SP
return r_dst;
@@ -1646,7 +1657,7 @@
PPCAMode* am_addr =3D PPCAMode_IR( e->Iex.Get.offset,
GuestStatePtr(mode64) );
addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),=20
- False, r_dst, am_addr, mode64 ));
+ r_dst, am_addr, mode64 ));
return r_dst;
}
break;
@@ -1659,7 +1670,7 @@
e->Iex.GetI.ix, e->Iex.GetI.bias=
);
HReg r_dst =3D newVRegI(env);
addInstr(env, PPCInstr_Load( toUChar(8),
- False, r_dst, src_am, mode64 ));
+ r_dst, src_am, mode64 ));
return r_dst;
}
break;
@@ -2370,8 +2381,8 @@
PPCAMode* am_addr4 =3D advance4(env, am_addr);
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
- addInstr(env, PPCInstr_Load( 4, False, tHi, am_addr, False/*mode3=
2*/ ));
- addInstr(env, PPCInstr_Load( 4, False, tLo, am_addr4, False/*mode3=
2*/ ));
+ addInstr(env, PPCInstr_Load( 4, tHi, am_addr, False/*mode32*/ ));
+ addInstr(env, PPCInstr_Load( 4, tLo, am_addr4, False/*mode32*/ ));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2521,9 +2532,9 @@
=20
// load hi,lo words (of hi/lo half of vec) as Ity_I32's
addInstr(env,
- PPCInstr_Load( 4, False, tHi, am_offHI, False/*mode32*=
/ ));
+ PPCInstr_Load( 4, tHi, am_offHI, False/*mode32*/ ));
addInstr(env,
- PPCInstr_Load( 4, False, tLo, am_offLO, False/*mode32*=
/ ));
+ PPCInstr_Load( 4, tLo, am_offLO, False/*mode32*/ ));
=20
add_to_sp( env, 32 ); // Reset SP
*rHi =3D tHi;
@@ -2581,9 +2592,9 @@
fr_src, am_addr0 ));
=20
// load hi,lo as Ity_I32's
- addInstr(env, PPCInstr_Load( 4, False, r_dstHi,
+ addInstr(env, PPCInstr_Load( 4, r_dstHi,
am_addr0, False/*mode32*/ ));
- addInstr(env, PPCInstr_Load( 4, False, r_dstLo,
+ addInstr(env, PPCInstr_Load( 4, r_dstLo,
am_addr1, False/*mode32*/ ));
*rHi =3D r_dstHi;
*rLo =3D r_dstLo;
@@ -2782,21 +2793,28 @@
}
=20
if (e->Iex.Binop.op =3D=3D Iop_I64toF64) {
- HReg fr_dst =3D newVRegF(env);
- HReg r_src =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
- vassert(mode64);
+ if (mode64) {
+ HReg fdst =3D newVRegF(env);
+ HReg isrc =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
+ HReg r1 =3D StackFramePtr(env->mode64);
+ PPCAMode* zero_r1 =3D PPCAMode_IR( 0, r1 );
=20
- /* Set host rounding mode */
- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+ /* Set host rounding mode */
+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
- sub_from_sp( env, 16 );
-vassert(0);
-// addInstr(env, PPCInstr_FpI64toF64(fr_dst, r_src));
- add_to_sp( env, 16 );
+ sub_from_sp( env, 16 );
=20
- /* Restore default FPU rounding. */
- set_FPU_rounding_default( env );
- return fr_dst;
+ addInstr(env, PPCInstr_Store(8, zero_r1, isrc, True/*mode64*=
/));
+ addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1=
));
+ addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,=20
+ fdst, fdst));
+
+ add_to_sp( env, 16 );
+
+ /* Restore default FPU rounding. */
+ set_FPU_rounding_default( env );
+ return fdst;
+ }
}
}
=20
|