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From: <sv...@va...> - 2006-01-05 13:12:21
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Author: cerion
Date: 2006-01-05 13:11:59 +0000 (Thu, 05 Jan 2006)
New Revision: 1532
Log:
ppc: deal with L flag properly for different sync forms.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-01-04 10:53:00 UTC (rev 1531)
+++ trunk/priv/guest-ppc/toIR.c 2006-01-05 13:11:59 UTC (rev 1532)
@@ -4428,6 +4428,8 @@
/* X-Form, XL-Form */
UChar opc1 =3D ifieldOPC(theInstr);
UInt b11to25 =3D IFIELD(theInstr, 11, 15);
+ UChar flag_L =3D ifieldRegDS(theInstr);
+ UInt b11to20 =3D IFIELD(theInstr, 11, 10);
UChar rD_addr =3D ifieldRegDS(theInstr);
UChar rS_addr =3D rD_addr;
UChar rA_addr =3D ifieldRegA(theInstr);
@@ -4522,7 +4524,7 @@
}
=20
case 0x256: // sync (Synchronize, PPC32 p543),=20
- // also lwsync, which appears to be undocumented
+ // also lwsync (L=3D=3D1), ptesync (L=3D=3D2)
/* http://sources.redhat.com/ml/binutils/2000-12/msg00311.html
=20
The PowerPC architecture used in IBM chips has expanded
@@ -4542,12 +4544,17 @@
=20
sync =3D sync 0
lwsync =3D sync 1
+ ptesync =3D sync 2 *** TODO - not implemented ***
*/
- if ((b11to25 !=3D 0/*sync*/ && b11to25 !=3D 1024/*lwsync*/) || =
b0 !=3D 0) {
- vex_printf("dis_memsync(ppc)(sync/lwsync,b11to25|b0)\n");
+ if (b11to20 !=3D 0 || b0 !=3D 0) {
+ vex_printf("dis_memsync(ppc)(sync/lwsync,b11to20|b0)\n");
return False;
}
- DIP("%ssync\n", b11to25 =3D=3D 1024 ? "lw" : "");
+ if (flag_L !=3D 0/*sync*/ && flag_L !=3D 1/*lwsync*/) {
+ vex_printf("dis_memsync(ppc)(sync/lwsync,flag_L)\n");
+ return False;
+ }
+ DIP("%ssync\n", flag_L =3D=3D 1 ? "lw" : "");
/* Insert a memory fence. It's sometimes important that these
are carried through to the generated code. */
stmt( IRStmt_MFence() );
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