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From: <sv...@va...> - 2005-12-24 12:39:50
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Author: cerion
Date: 2005-12-24 12:39:47 +0000 (Sat, 24 Dec 2005)
New Revision: 1510
Log:
Put mode64 in ISelEnv, removing global variable.
Modified:
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2005-12-24 12:32:10 UTC (rev 1509)
+++ trunk/priv/host-ppc/isel.c 2005-12-24 12:39:47 UTC (rev 1510)
@@ -54,13 +54,10 @@
#include "host-generic/h_generic_regs.h"
#include "host-ppc/hdefs.h"
=20
-/* Is our guest binary 32 or 64bit? Set at each call to
- iselBB_PPC below. */
-static Bool mode64 =3D False;
+/* GPR register class for ppc32/64 */
+#define HRcGPR(__mode64) (__mode64 ? HRcInt64 : HRcInt32)
=20
-#define HRcIntWRDSZ (mode64 ? HRcInt64 : HRcInt32)
=20
-
/*---------------------------------------------------------*/
/*--- Register Usage Conventions ---*/
/*---------------------------------------------------------*/
@@ -192,8 +189,11 @@
- The host subarchitecture we are selecting insns for. =20
This is set at the start and does not change.
=20
- Note, this is all host-independent. (JRS 20050201: well, kinda
- ... not completely. Compare with ISelEnv for amd64.)
+ - A Bool to tell us if the host is 32 or 64bit.
+ This is set at the start and does not change.
+=20
+ Note, this is mostly host-independent.
+ (JRS 20050201: well, kinda... Compare with ISelEnv for amd64.)
*/
=20
typedef
@@ -211,6 +211,8 @@
Int vreg_ctr;
=20
VexSubArch subarch;
+
+ Bool mode64;
}
ISelEnv;
=20
@@ -225,7 +227,7 @@
static void lookupIRTemp64 ( HReg* vrHI, HReg* vrLO,
ISelEnv* env, IRTemp tmp )
{
- vassert(!mode64);
+ vassert(!env->mode64);
vassert(tmp >=3D 0);
vassert(tmp < env->n_vregmap);
vassert(env->vregmapHI[tmp] !=3D INVALID_HREG);
@@ -236,7 +238,7 @@
static void lookupIRTemp128 ( HReg* vrHI, HReg* vrLO,
ISelEnv* env, IRTemp tmp )
{
- vassert(mode64);
+ vassert(env->mode64);
vassert(tmp >=3D 0);
vassert(tmp < env->n_vregmap);
vassert(env->vregmapHI[tmp] !=3D INVALID_HREG);
@@ -248,14 +250,15 @@
{
addHInstr(env->code, instr);
if (vex_traceflags & VEX_TRACE_VCODE) {
- ppPPCInstr(instr, mode64);
+ ppPPCInstr(instr, env->mode64);
vex_printf("\n");
}
}
=20
static HReg newVRegI ( ISelEnv* env )
{ =20
- HReg reg =3D mkHReg(env->vreg_ctr, HRcIntWRDSZ, True/*virtual reg*/);
+ HReg reg =3D mkHReg(env->vreg_ctr, HRcGPR(env->mode64),
+ True/*virtual reg*/);
env->vreg_ctr++;
return reg;
}
@@ -361,8 +364,9 @@
=20
static PPCInstr* mk_iMOVds_RR ( HReg r_dst, HReg r_src )
{
- vassert(hregClass(r_dst) =3D=3D HRcIntWRDSZ);
- vassert(hregClass(r_src) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(r_dst) =3D=3D hregClass(r_src));
+ vassert(hregClass(r_src) =3D=3D HRcInt32 ||
+ hregClass(r_src) =3D=3D HRcInt64);
return PPCInstr_Alu(Palu_OR, r_dst, r_src, PPCRH_Reg(r_src));
}
=20
@@ -379,7 +383,7 @@
=20
static void add_to_sp ( ISelEnv* env, UInt n )
{
- HReg sp =3D StackFramePtr(mode64);
+ HReg sp =3D StackFramePtr(env->mode64);
vassert(n < 256 && (n%16) =3D=3D 0);
addInstr(env, PPCInstr_Alu( Palu_ADD, sp, sp,
PPCRH_Imm(True,toUShort(n)) ));
@@ -387,7 +391,7 @@
=20
static void sub_from_sp ( ISelEnv* env, UInt n )
{
- HReg sp =3D StackFramePtr(mode64);
+ HReg sp =3D StackFramePtr(env->mode64);
vassert(n < 256 && (n%16) =3D=3D 0);
addInstr(env, PPCInstr_Alu( Palu_SUB, sp, sp,
PPCRH_Imm(True,toUShort(n)) ));
@@ -403,12 +407,13 @@
{
HReg r =3D newVRegI(env);
HReg align16 =3D newVRegI(env);
- addInstr(env, mk_iMOVds_RR(r, StackFramePtr(mode64)));
+ addInstr(env, mk_iMOVds_RR(r, StackFramePtr(env->mode64)));
// add 16
addInstr(env, PPCInstr_Alu( Palu_ADD, r, r,
PPCRH_Imm(True,toUShort(16)) ));
// mask to quadword
- addInstr(env, PPCInstr_LI(align16, 0xFFFFFFFFFFFFFFF0ULL, mode64));
+ addInstr(env,
+ PPCInstr_LI(align16, 0xFFFFFFFFFFFFFFF0ULL, env->mode64));
addInstr(env, PPCInstr_Alu(Palu_AND, r,r, PPCRH_Reg(align16)));
return r;
}
@@ -422,17 +427,17 @@
HReg fr_dst =3D newVRegF(env);
PPCAMode *am_addr0, *am_addr1;
=20
- vassert(!mode64);
+ vassert(!env->mode64);
vassert(hregClass(r_srcHi) =3D=3D HRcInt32);
vassert(hregClass(r_srcLo) =3D=3D HRcInt32);
=20
sub_from_sp( env, 16 ); // Move SP down 16 bytes
- am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
- am_addr1 =3D PPCAMode_IR( 4, StackFramePtr(mode64) );
+ am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(env->mode64) );
+ am_addr1 =3D PPCAMode_IR( 4, StackFramePtr(env->mode64) );
=20
// store hi,lo as Ity_I32's
- addInstr(env, PPCInstr_Store( 4, am_addr0, r_srcHi, mode64 ));
- addInstr(env, PPCInstr_Store( 4, am_addr1, r_srcLo, mode64 ));
+ addInstr(env, PPCInstr_Store( 4, am_addr0, r_srcHi, env->mode64 ));
+ addInstr(env, PPCInstr_Store( 4, am_addr1, r_srcLo, env->mode64 ));
=20
// load as float
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, am_addr0));
@@ -447,14 +452,14 @@
HReg fr_dst =3D newVRegF(env);
PPCAMode *am_addr0;
=20
- vassert(mode64);
+ vassert(env->mode64);
vassert(hregClass(r_src) =3D=3D HRcInt64);
=20
sub_from_sp( env, 16 ); // Move SP down 16 bytes
- am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
+ am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(env->mode64) );
=20
// store as Ity_I64
- addInstr(env, PPCInstr_Store( 8, am_addr0, r_src, mode64 ));
+ addInstr(env, PPCInstr_Store( 8, am_addr0, r_src, env->mode64 ));
=20
// load as float
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, am_addr0));
@@ -512,6 +517,7 @@
Int n_args, i, argreg;
UInt argiregs;
ULong target;
+ Bool mode64 =3D env->mode64;
=20
/* Marshal args for a call and do the call.
=20
@@ -741,8 +747,8 @@
- so we can set the whole register at once (faster)
note: upper 32 bits ignored by FpLdFPSCR
*/
- addInstr(env, PPCInstr_LI(r_src, 0x0, mode64));
- if (mode64) {
+ addInstr(env, PPCInstr_LI(r_src, 0x0, env->mode64));
+ if (env->mode64) {
fr_src =3D mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
} else {
fr_src =3D mk_LoadRR32toFPR( env, r_src, r_src ); // 2*I32 -> F64
@@ -764,7 +770,7 @@
HReg r_rmPPC =3D newVRegI(env);
HReg r_tmp =3D newVRegI(env);
=20
- vassert(hregClass(r_rmIR) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(r_rmIR) =3D=3D HRcGPR(env->mode64));
=20
// AND r_rmIR,3 -- shouldn't be needed; paranoia
addInstr(env, PPCInstr_Alu( Palu_AND, r_rmIR, r_rmIR,
@@ -802,7 +808,7 @@
// Resolve rounding mode and convert to PPC representation
r_src =3D roundModeIRtoPPC( env, iselIntExpr_R(env, mode) );
// gpr -> fpr
- if (mode64) {
+ if (env->mode64) {
fr_src =3D mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
} else {
fr_src =3D mk_LoadRR32toFPR( env, r_src, r_src ); // 2*I32 -> F64
@@ -900,7 +906,7 @@
=20
/* no luck; use the Slow way. */
r_src =3D newVRegI(env);
- addInstr(env, PPCInstr_LI(r_src, (Long)simm32, mode64));
+ addInstr(env, PPCInstr_LI(r_src, (Long)simm32, env->mode64));
}
else {
r_src =3D ri->Pri.Reg;
@@ -921,7 +927,7 @@
am_off12 =3D PPCAMode_IR( 12, r_aligned16 );
=20
/* Store r_src in low word of 16-aligned mem */
- addInstr(env, PPCInstr_Store( 4, am_off12, r_src, mode64 ));
+ addInstr(env, PPCInstr_Store( 4, am_off12, r_src, env->mode64 ));
=20
/* Load src to vector[low lane] */
addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, v_src, am_off12 ) );
@@ -987,7 +993,7 @@
vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
# endif
=20
- vassert(hregClass(r) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(r) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(r));
return r;
}
@@ -995,6 +1001,7 @@
/* DO NOT CALL THIS DIRECTLY ! */
static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
{
+ Bool mode64 =3D env->mode64;
MatchInfo mi;
DECLARE_PATTERN(p_32to1_then_1Uto8);
=20
@@ -1790,17 +1797,18 @@
return toBool(u =3D=3D (UInt)i);
}
=20
-static Bool sane_AMode ( PPCAMode* am )
+static Bool sane_AMode ( ISelEnv* env, PPCAMode* am )
{
+ Bool mode64 =3D env->mode64;
switch (am->tag) {
case Pam_IR:
- return toBool( hregClass(am->Pam.IR.base) =3D=3D HRcIntWRDSZ &&=20
+ return toBool( hregClass(am->Pam.IR.base) =3D=3D HRcGPR(mode64) &&=
=20
hregIsVirtual(am->Pam.IR.base) &&=20
fits16bits(am->Pam.IR.index) );
case Pam_RR:
- return toBool( hregClass(am->Pam.RR.base) =3D=3D HRcIntWRDSZ &&=20
- hregIsVirtual(am->Pam.IR.base) &&
- hregClass(am->Pam.RR.index) =3D=3D HRcIntWRDSZ &&
+ return toBool( hregClass(am->Pam.RR.base) =3D=3D HRcGPR(mode64) &&=
=20
+ hregIsVirtual(am->Pam.RR.base) &&
+ hregClass(am->Pam.RR.index) =3D=3D HRcGPR(mode64) &=
&
hregIsVirtual(am->Pam.IR.index) );
default:
vpanic("sane_AMode: unknown ppc amode tag");
@@ -1810,7 +1818,7 @@
static PPCAMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e )
{
PPCAMode* am =3D iselIntExpr_AMode_wrk(env, e);
- vassert(sane_AMode(am));
+ vassert(sane_AMode(env, am));
return am;
}
=20
@@ -1818,7 +1826,7 @@
static PPCAMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
- vassert(ty =3D=3D (mode64 ? Ity_I64 : Ity_I32));
+ vassert(ty =3D=3D (env->mode64 ? Ity_I64 : Ity_I32));
=20
/* Add32(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
if (e->tag =3D=3D Iex_Binop=20
@@ -1866,7 +1874,7 @@
vassert(ri->Prh.Imm.imm16 !=3D 0x8000);
return ri;
case Prh_Reg:
- vassert(hregClass(ri->Prh.Reg.reg) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(ri->Prh.Reg.reg) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(ri->Prh.Reg.reg));
return ri;
default:
@@ -1881,7 +1889,7 @@
Long l;
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 ||
- ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64));
+ ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && env->mode64));
=20
/* special case: immediate */
if (e->tag =3D=3D Iex_Const) {
@@ -1889,7 +1897,7 @@
/* What value are we aiming to generate? */
switch (con->tag) {
/* Note: Not sign-extending - we carry 'syned' around */
- case Ico_U64: vassert(mode64);
+ case Ico_U64: vassert(env->mode64);
u =3D con->Ico.U64; break;
case Ico_U32: u =3D 0xFFFFFFFF & con->Ico.U32; break;
case Ico_U16: u =3D 0x0000FFFF & con->Ico.U16; break;
@@ -1928,7 +1936,7 @@
case Pri_Imm:
return ri;
case Pri_Reg:
- vassert(hregClass(ri->Pri.Reg) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(ri->Pri.Reg) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(ri->Pri.Reg));
return ri;
default:
@@ -1942,13 +1950,13 @@
Long l;
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 ||
- ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64));
+ ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && env->mode64));
=20
/* special case: immediate */
if (e->tag =3D=3D Iex_Const) {
IRConst* con =3D e->Iex.Const.con;
switch (con->tag) {
- case Ico_U64: vassert(mode64);
+ case Ico_U64: vassert(env->mode64);
l =3D (Long) con->Ico.U64; break;
case Ico_U32: l =3D (Long)(Int) con->Ico.U32; break;
case Ico_U16: l =3D (Long)(Int)(Short)con->Ico.U16; break;
@@ -1982,7 +1990,7 @@
vassert(!ri->Prh.Imm.syned);
return ri;
case Prh_Reg:
- vassert(hregClass(ri->Prh.Reg.reg) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(ri->Prh.Reg.reg) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(ri->Prh.Reg.reg));
return ri;
default:
@@ -2028,7 +2036,7 @@
vassert(!ri->Prh.Imm.syned);
return ri;
case Prh_Reg:
- vassert(hregClass(ri->Prh.Reg.reg) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(ri->Prh.Reg.reg) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(ri->Prh.Reg.reg));
return ri;
default:
@@ -2085,7 +2093,7 @@
if (e->tag =3D=3D Iex_Const && e->Iex.Const.con->Ico.U1 =3D=3D True) =
{
// Make a compare that will always be true:
HReg r_zero =3D newVRegI(env);
- addInstr(env, PPCInstr_LI(r_zero, 0, mode64));
+ addInstr(env, PPCInstr_LI(r_zero, 0, env->mode64));
addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
7/*cr*/, r_zero, PPCRH_Reg(r_zero)));
return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
@@ -2241,7 +2249,7 @@
e->Iex.Binop.op =3D=3D Iop_CmpLE64S);
HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
PPCRH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
- vassert(mode64);
+ vassert(env->mode64);
addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
7/*cr*/, r1, ri2));
=20
@@ -2307,7 +2315,7 @@
/* CmpNEZ64 */
if (e->tag =3D=3D Iex_Unop=20
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
- if (!mode64) {
+ if (!env->mode64) {
HReg hi, lo;
HReg tmp =3D newVRegI(env);
iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg );
@@ -2355,14 +2363,14 @@
static void iselInt128Expr ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
{
- vassert(mode64);
+ vassert(env->mode64);
iselInt128Expr_wrk(rHi, rLo, env, e);
# if 0
vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
# endif
- vassert(hregClass(*rHi) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(*rHi) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(*rHi));
- vassert(hregClass(*rLo) =3D=3D HRcIntWRDSZ);
+ vassert(hregClass(*rLo) =3D=3D HRcGPR(env->mode64));
vassert(hregIsVirtual(*rLo));
}
=20
@@ -2439,7 +2447,7 @@
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
{
- vassert(!mode64);
+ vassert(!env->mode64);
iselInt64Expr_wrk(rHi, rLo, env, e);
# if 0
vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
@@ -2454,6 +2462,7 @@
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
{
+ Bool mode64 =3D env->mode64;
// HWord fn =3D 0; /* helper fn for most SIMD64 stuff */
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) =3D=3D Ity_I64);
@@ -3168,7 +3177,7 @@
if (e->tag =3D=3D Iex_Get) {
HReg r_dst =3D newVRegF(env);
PPCAMode* am_addr =3D PPCAMode_IR( e->Iex.Get.offset,
- GuestStatePtr(mode64) );
+ GuestStatePtr(env->mode64) );
addInstr(env, PPCInstr_FpLdSt( True/*load*/, 4, r_dst, am_addr ));
return r_dst;
}
@@ -3235,6 +3244,7 @@
/* DO NOT CALL THIS DIRECTLY */
static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
{
+ Bool mode64 =3D env->mode64;
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(e);
vassert(ty =3D=3D Ity_F64);
@@ -3482,6 +3492,7 @@
/* DO NOT CALL THIS DIRECTLY */
static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
{
+ Bool mode64 =3D env->mode64;
//.. Bool arg1isEReg =3D False;
PPCAvOp op =3D Pav_INVALID;
IRType ty =3D typeOfIRExpr(env->type_env,e);
@@ -4089,6 +4100,7 @@
=20
static void iselStmt ( ISelEnv* env, IRStmt* stmt )
{
+ Bool mode64 =3D env->mode64;
if (vex_traceflags & VEX_TRACE_VCODE) {
vex_printf("\n -- ");
ppIRStmt(stmt);
@@ -4393,6 +4405,7 @@
HReg hreg, hregHI;
ISelEnv* env;
VexSubArch subarch_host =3D archinfo_host->subarch;
+ Bool mode64;
=20
/* Figure out whether we're being ppc32 or ppc64 today. */
switch (subarch_host) {
@@ -4413,6 +4426,9 @@
env =3D LibVEX_Alloc(sizeof(ISelEnv));
env->vreg_ctr =3D 0;
=20
+ /* Are we being ppc32 or ppc64? */
+ env->mode64 =3D mode64;
+
/* Set up output code array. */
env->code =3D newHInstrArray();
=20
|