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From: <sv...@va...> - 2005-12-24 12:32:17
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Author: cerion
Date: 2005-12-24 12:32:10 +0000 (Sat, 24 Dec 2005)
New Revision: 1509
Log:
Fix AltiVec load/store on ppc64 - was only considering lo32 bits of addre=
ss.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2005-12-23 12:46:16 UTC (rev 1508)
+++ trunk/priv/guest-ppc/toIR.c 2005-12-24 12:32:10 UTC (rev 1509)
@@ -1145,8 +1145,7 @@
}
=20
vassert(typeOfIRExpr(irbb->tyenv,addr) =3D=3D ty);
- return binop( mkSzOp(ty, Iop_And8),
- addr, mkSzImm(ty, mask) );
+ return binop( mkSzOp(ty, Iop_And8), addr, mkSzImm(ty, mask) );
}
=20
=20
@@ -6306,27 +6305,28 @@
UInt opc2 =3D ifieldOPClo10(theInstr);
UChar b0 =3D ifieldBIT0(theInstr);
=20
- IRType ty =3D mode64 ? Ity_I64 : Ity_I32;
- IRTemp EA_lo32 =3D newTemp(Ity_I32);
- IRTemp addr_align16 =3D newTemp(ty);
+ IRType ty =3D mode64 ? Ity_I64 : Ity_I32;
+ IRTemp EA =3D newTemp(ty);
+ IRTemp EA_align16 =3D newTemp(ty);
=20
if (opc1 !=3D 0x1F || b0 !=3D 0) {
vex_printf("dis_av_load(ppc)(instr)\n");
return False;
}
=20
- assign( EA_lo32, mkSzNarrow32(ty, ea_rAor0_idxd(rA_addr, rB_addr)) );
- assign( addr_align16, addr_align( mkexpr(EA_lo32), 16 ) );
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+ assign( EA_align16, addr_align( mkexpr(EA), 16 ) );
=20
switch (opc2) {
=20
case 0x006: { // lvsl (Load Vector for Shift Left, AV p123)
+ IRDirty* d;
UInt vD_off =3D vectorGuestRegOffset(vD_addr);
IRExpr** args =3D mkIRExprVec_3(
mkU32(vD_off),=20
- binop(Iop_And32, mkexpr(EA_lo32), mkU32(0xF)),
+ binop(Iop_And32, mkSzNarrow32(ty, mkexpr(EA)),
+ mkU32(0xF)),
mkU32(0)/*left*/ );
- IRDirty* d;
if (!mode64) {
d =3D unsafeIRDirty_0_N ( 0/*regparms*/,=20
"ppc32g_dirtyhelper_LVS",
@@ -6351,12 +6351,13 @@
break;
}
case 0x026: { // lvsr (Load Vector for Shift Right, AV p125)
+ IRDirty* d;
UInt vD_off =3D vectorGuestRegOffset(vD_addr);
IRExpr** args =3D mkIRExprVec_3(
mkU32(vD_off),=20
- binop(Iop_And32, mkexpr(EA_lo32), mkU32(0xF)),
+ binop(Iop_And32, mkSzNarrow32(ty, mkexpr(EA)),
+ mkU32(0xF)),
mkU32(1)/*right*/ );
- IRDirty* d;
if (!mode64) {
d =3D unsafeIRDirty_0_N ( 0/*regparms*/,=20
"ppc32g_dirtyhelper_LVS",
@@ -6385,24 +6386,24 @@
/* loads addressed byte into vector[EA[0:3]
since all other destination bytes are undefined,
can simply load entire vector from 16-aligned EA */
- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(addr_align16)) );
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
break;
=20
case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121)
DIP("lvehx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
/* see note for lvebx */
- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(addr_align16)) );
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
break;
=20
case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122)
DIP("lvewx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
/* see note for lvebx */
- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(addr_align16)) );
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
break;
=20
case 0x067: // lvx (Load Vector Indexed, AV p127)
DIP("lvx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(addr_align16)) );
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
break;
=20
case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
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