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From: <sv...@va...> - 2005-11-19 19:27:15
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Author: sewardj
Date: 2005-11-19 19:27:06 +0000 (Sat, 19 Nov 2005)
New Revision: 5208
Log:
Fix up the test program so it behaves the same on different CPUs (when ru=
n
natively):
- register_vfarg: stuff bits directly into vector, don't go via float
as that screws up NaNs somehow on MPC7447
- test_av_int_ld_two_regs: lve{b,h,w}x: mask off bits of the result=20
register which are undefined after the load
- test_av_int_st_three_regs: fix result vector size
Modified:
trunk/none/tests/ppc32/jm-insns.c
Modified: trunk/none/tests/ppc32/jm-insns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/jm-insns.c 2005-11-19 15:31:13 UTC (rev 5207)
+++ trunk/none/tests/ppc32/jm-insns.c 2005-11-19 19:27:06 UTC (rev 5208)
@@ -3917,10 +3917,12 @@
int s, uint8_t exp, uint32_t mant)
{
uint32_t tmp;
- =20
+ vector uint32_t* vfargI =3D (vector uint32_t*)vfarg;
+
tmp =3D ((uint64_t)s << 31) | ((uint64_t)exp << 23) | mant;
- float f =3D *(float*)&tmp;
- *vfarg =3D (vector float){ f,f,f,f };
+ //float f =3D *(float*)&tmp;
+ //*vfarg =3D (vector float){ f,f,f,f };
+ *vfargI =3D (vector uint32_t){ tmp,tmp,tmp,tmp };
AB_DPRINTF("%d %02x %06x =3D> %08x %0e\n",
s, exp, mant, *((uint32_t*)&tmp), f);
}
@@ -6115,8 +6117,13 @@
{
volatile uint32_t flags, tmpcr;
volatile vector unsigned int tmpvscr;
- int i,j;
+ int i,j, k, do_mask;
=20
+ do_mask =3D 0;
+ if (strstr(name, "lvebx")) do_mask =3D 1;
+ if (strstr(name, "lvehx")) do_mask =3D 2;
+ if (strstr(name, "lvewx")) do_mask =3D 4;
+
for (i=3D0; i<nb_viargs; i++) {
for (j=3D0; j<16; j+=3D7) {
volatile vector unsigned int vec_out =3D (vector unsigned int){=
0,0,0,0 };
@@ -6134,7 +6141,7 @@
flags =3D 0;
__asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
- =20
+
// do stuff
(*func)();
=20
@@ -6152,6 +6159,31 @@
volatile vector unsigned int vec_in =3D (vector unsigned int)vi=
args[i];
unsigned int* src =3D (unsigned int*)&vec_in;
unsigned int* dst =3D (unsigned int*)&vec_out;
+
+ /* For lvebx/lvehx/lvewx, as per the documentation, all of
+ the dest reg except the loaded bits are undefined
+ afterwards. And different CPUs really do produce
+ different results. So mask out bits of the result that
+ are undefined so as to make the test work reliably. */
+ if (do_mask =3D=3D 1) {
+ char* p =3D (char*)dst;
+ for (k =3D 0; k < 16; k++)
+ if (k !=3D j)
+ p[k] =3D (char)0;
+ }
+ if (do_mask =3D=3D 2) {
+ short* p =3D (short*)dst;
+ for (k =3D 0; k < 8; k++)
+ if (k !=3D (j>>1))
+ p[k] =3D (short)0;
+ }
+ if (do_mask =3D=3D 4) {
+ int* p =3D (int*)dst;
+ for (k =3D 0; k < 4; k++)
+ if (k !=3D (j>>2))
+ p[k] =3D (int)0;
+ }
+
printf("%s %3d, %08x %08x %08x %08x", name, j, src[0], src[1], =
src[2], src[3]);
printf(" =3D> %08x %08x %08x %08x ", dst[0], dst[1], dst[2], ds=
t[3]);
printf("(%08x)\n", flags);
@@ -6171,7 +6203,7 @@
vector unsigned int* viargs_priv;
=20
// private viargs table to store to
- viargs_priv =3D memalign(16,(nb_viargs * sizeof(uint32_t)));
+ viargs_priv =3D memalign(16,(nb_viargs * sizeof(vector unsigned int))=
);
for (i=3D0; i<nb_viargs; i++)
viargs_priv[i] =3D (vector unsigned int) { 0,0,0,0 };
=20
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