From: <sv...@va...> - 2005-11-13 20:30:29
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Author: sewardj Date: 2005-11-13 20:30:24 +0000 (Sun, 13 Nov 2005) New Revision: 1454 Log: More profiling-induced speedups. Modified: trunk/priv/guest-amd64/ghelpers.c Modified: trunk/priv/guest-amd64/ghelpers.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/priv/guest-amd64/ghelpers.c 2005-11-13 19:51:04 UTC (rev 1453) +++ trunk/priv/guest-amd64/ghelpers.c 2005-11-13 20:30:24 UTC (rev 1454) @@ -1021,6 +1021,19 @@ binop(Iop_CmpEQ64, cc_dep1, mkU64(0))); } =20 + if (isU64(cc_op, AMD64G_CC_OP_LOGICQ) && isU64(cond, AMD64CondL)) = { + /* long long and/or/xor, then L + LOGIC sets SF and ZF according to the + result and makes OF be zero. L computes SF ^ OF, but + OF is zero, so this reduces to SF -- which will be 1 iff + the result is < signed 0. Hence ... + */ + return unop(Iop_1Uto64, + binop(Iop_CmpLT64S,=20 + cc_dep1,=20 + mkU64(0))); + } + /*---------------- LOGICL ----------------*/ =20 if (isU64(cc_op, AMD64G_CC_OP_LOGICL) && isU64(cond, AMD64CondZ)) = { @@ -1047,8 +1060,8 @@ if (isU64(cc_op, AMD64G_CC_OP_LOGICL) && isU64(cond, AMD64CondLE))= { /* long and/or/xor, then LE This is pretty subtle. LOGIC sets SF and ZF according to th= e - result and makes OF be zero. LE computes (SZ ^ OF) | ZF, bu= t - OF is zero, so this reduces to SZ | ZF -- which will be 1 if= f + result and makes OF be zero. LE computes (SF ^ OF) | ZF, bu= t + OF is zero, so this reduces to SF | ZF -- which will be 1 if= f the result is <=3Dsigned 0. Hence ... */ return unop(Iop_1Uto64, @@ -1094,6 +1107,16 @@ mkU64(0))); } =20 + /*---------------- DECL ----------------*/ + + if (isU64(cc_op, AMD64G_CC_OP_DECL) && isU64(cond, AMD64CondZ)) { + /* dec L, then Z --> test dst =3D=3D 0 */ + return unop(Iop_1Uto64, + binop(Iop_CmpEQ64, + binop(Iop_Shl64,cc_dep1,mkU8(32)), + mkU64(0))); + } + /*---------------- DECW ----------------*/ =20 if (isU64(cc_op, AMD64G_CC_OP_DECW) && isU64(cond, AMD64CondNZ)) { @@ -1184,6 +1207,13 @@ cc_dep2 =3D args[2]; cc_ndep =3D args[3]; =20 + if (isU64(cc_op, AMD64G_CC_OP_SUBQ)) { + /* C after sub denotes unsigned less than */ + return unop(Iop_1Uto64, + binop(Iop_CmpLT64U,=20 + cc_dep1, + cc_dep2)); + } if (isU64(cc_op, AMD64G_CC_OP_SUBL)) { /* C after sub denotes unsigned less than */ return unop(Iop_1Uto64, |