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From: <sv...@va...> - 2005-10-05 16:58:44
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Author: sewardj
Date: 2005-10-05 17:58:23 +0100 (Wed, 05 Oct 2005)
New Revision: 1413
Log:
Implement JRCXZ.
Modified:
trunk/priv/guest-amd64/toIR.c
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-10-05 10:39:58 UTC (rev 1412)
+++ trunk/priv/guest-amd64/toIR.c 2005-10-05 16:58:23 UTC (rev 1413)
@@ -11573,23 +11573,20 @@
DIP("j%s-8 0x%llx\n", name_AMD64Condcode(opc - 0x70), d64);
break;
=20
-//.. case 0xE3: /* JECXZ or perhaps JCXZ, depending on OSO ? Intel
-//.. manual says it depends on address size override,
-//.. which doesn't sound right to me. */
-//.. vassert(sz=3D=3D4); /* possibly also OK for sz=3D=3D2 */
-//.. d32 =3D (((Addr32)guest_eip_bbstart)+delta+1) + getSDisp8(del=
ta);
-//.. delta++;
-//.. ty =3D szToITy(sz);
-//.. stmt( IRStmt_Exit(
-//.. binop(mkSizedOp(ty,Iop_CmpEQ8),
-//.. getIReg(sz,R_ECX),
-//.. mkU(ty,0)),
-//.. Ijk_Boring,
-//.. IRConst_U32(d32))=20
-//.. );
-//..=20
-//.. DIP("j%sz 0x%x\n", nameIReg(sz, R_ECX), d32);
-//.. break;
+ case 0xE3: /* JRCXZ or perhaps JECXZ, depending on OSO ? Intel
+ manual says it depends on address size override,
+ which doesn't sound right to me. But the amd manual
+ alsay says that, so I guess it is. In which case 8
+ is the only valid size. */
+ if (have66orF2orF3(pfx) || haveASO(pfx)) goto decode_failure;
+ d64 =3D (guest_RIP_bbstart+delta+1) + getSDisp8(delta);=20
+ delta++;
+ stmt( IRStmt_Exit( binop(Iop_CmpEQ64, getIReg64(R_RCX), mkU64(0)),
+ Ijk_Boring,
+ IRConst_U64(d64))=20
+ );
+ DIP("jrcxz 0x%llx\n", d64);
+ break;
=20
case 0xE0: /* LOOPNE disp8: decrement count, jump if count !=3D 0 && =
ZF=3D=3D0 */
case 0xE1: /* LOOPE disp8: decrement count, jump if count !=3D 0 && =
ZF=3D=3D1 */
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