[Valgrind-developers] valgrind: r4636 - in trunk/coregrind: . m_dispatch

[<sv...@va...>]

Author: cerion
Date: 2005-09-13 12:13:43 +0100 (Tue, 13 Sep 2005)
New Revision: 4636

Log:
setup new variable VG_(have_altivec) from auxv::AT_HWCAP
fixed default VSCR in dispatch-ppc32.S (non-java mode =3D 1)

Modified:
   trunk/coregrind/m_dispatch/dispatch-ppc32.S
   trunk/coregrind/m_machine.c
   trunk/coregrind/m_main.c
   trunk/coregrind/m_translate.c
   trunk/coregrind/pub_core_machine.h


Modified: trunk/coregrind/m_dispatch/dispatch-ppc32.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_dispatch/dispatch-ppc32.S	2005-09-13 08:42:48 UTC (=
rev 4635)
+++ trunk/coregrind/m_dispatch/dispatch-ppc32.S	2005-09-13 11:13:43 UTC (=
rev 4636)
@@ -92,9 +92,16 @@
=20
 	/* set host AltiVec control word to the default mode expected=20
 	   by VEX-generated code. */
-        vsubuwm 3,3,3   /* generate zero */
+        lis     3,VG_(have_altivec)@ha
+        lwz     3,VG_(have_altivec)@l(3)
+        cmplwi  3,0
+        beq     L1
+        /* generate vector {0x0,0x0,0x0,0x00010000} */
+        vspltisw 3,0x1      /* 4x 0x00000001 */
+        vspltisw 4,0x0      /* generate zero */
+        vsldoi  3,4,3,0x6   /* v3 =3D v3 >> 10 bytes */
         mtvscr  3
-
+L1:
         /* make a stack frame for the code we are calling */
         stwu    1,-16(1)
=20

Modified: trunk/coregrind/m_machine.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_machine.c	2005-09-13 08:42:48 UTC (rev 4635)
+++ trunk/coregrind/m_machine.c	2005-09-13 11:13:43 UTC (rev 4636)
@@ -214,11 +214,13 @@
 //////////////////////////////////////////////////////////////////
 // Architecture specifics
=20
+#if defined(VGA_ppc32)
 // PPC: what is the cache line size (for dcbz etc) ?  This info is
 // harvested on Linux at startup from the AT_SYSINFO entries.  0 means
 // not-yet-set.
-#if defined(VGA_ppc32)
 Int VG_(cache_line_size_ppc32) =3D 0;
+// Altivec enabled?  Harvested on startup from the AT_HWCAP entry
+Int VG_(have_altivec) =3D 0;
 #endif
=20
 // X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store

Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c	2005-09-13 08:42:48 UTC (rev 4635)
+++ trunk/coregrind/m_main.c	2005-09-13 11:13:43 UTC (rev 4636)
@@ -181,9 +181,10 @@
          break;
=20
       case AT_HWCAP:
-         VG_(debugLog)(1, "main", "PPC32 hwcaps(1): 0x%x\n", (UInt)auxv-=
>u.a_val);
-         auxv->u.a_val &=3D ~0x10000000; /* claim there is no Altivec su=
pport */
-         VG_(debugLog)(1, "main", "PPC32 hwcaps(2): 0x%x\n", (UInt)auxv-=
>u.a_val);
+         VG_(debugLog)(1, "main", "PPC32 hwcaps: 0x%x\n", (UInt)auxv->u.=
a_val);
+         if ((auxv->u.a_val & 0x10000000) > 0)
+            VG_(have_altivec) =3D 1;
+         VG_(debugLog)(1, "main", "PPC32 AltiVec support: %u\n", VG_(hav=
e_altivec));
          break;
 #     endif
=20

Modified: trunk/coregrind/m_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_translate.c	2005-09-13 08:42:48 UTC (rev 4635)
+++ trunk/coregrind/m_translate.c	2005-09-13 11:13:43 UTC (rev 4636)
@@ -34,6 +34,7 @@
 #include "pub_core_aspacemgr.h"
 #include "pub_core_cpuid.h"
 #include "pub_core_machine.h"       // For VG_(cache_line_size_ppc32)
+                                    // and VG_(have_altivec)
                                     // and VG_(get_SP)
                                     // and VG_(have_mxcsr_x86)
 #include "pub_core_libcbase.h"
@@ -112,7 +113,8 @@
=20
 #elif defined(VGA_ppc32)
    *vex_arch    =3D VexArchPPC32;
-   vai->subarch =3D VexSubArchPPC32_noAV;
+   vai->subarch =3D VG_(have_altivec) ? VexSubArchPPC32_AV
+                                    : VexSubArchPPC32_noAV;
    vai->ppc32_cache_line_szB =3D VG_(cache_line_size_ppc32);
    return True;
=20

Modified: trunk/coregrind/pub_core_machine.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_machine.h	2005-09-13 08:42:48 UTC (rev 4635)
+++ trunk/coregrind/pub_core_machine.h	2005-09-13 11:13:43 UTC (rev 4636)
@@ -78,11 +78,13 @@
=20
 // Architecture specifics
=20
+#if defined(VGA_ppc32)
 // PPC: what is the cache line size (for dcbz etc) ?
 // This info is harvested on Linux at startup from the AT_SYSINFO
 // entries.
-#if defined(VGA_ppc32)
 extern Int VG_(cache_line_size_ppc32);
+// Altivec enabled?  Harvested on startup from the AT_HWCAP entry
+extern Int VG_(have_altivec);
 #endif
=20
 // X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store