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From: <sv...@va...> - 2005-08-14 00:20:52
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Author: sewardj
Date: 2005-08-14 01:20:46 +0100 (Sun, 14 Aug 2005)
New Revision: 1335
Log:
merge r1333 (amd64 isel handle Sar16)
Modified:
branches/VEX_3_0_BRANCH/priv/host-amd64/isel.c
Modified: branches/VEX_3_0_BRANCH/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_0_BRANCH/priv/host-amd64/isel.c 2005-08-14 00:09:58 UT=
C (rev 1334)
+++ branches/VEX_3_0_BRANCH/priv/host-amd64/isel.c 2005-08-14 00:20:46 UT=
C (rev 1335)
@@ -913,14 +913,14 @@
case Iop_Shr32:
addInstr(env, AMD64Instr_MovZLQ(dst,dst));
break;
-//.. case Iop_Sar8:
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 24, X86RM_Reg(d=
st)));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 24, X86RM_Reg(d=
st)));
-//.. break;
-//.. case Iop_Sar16:
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 16, X86RM_Reg(d=
st)));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 16, X86RM_Reg(d=
st)));
-//.. break;
+ case Iop_Sar8:
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, 56, dst));
+ break;
+ case Iop_Sar16:
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 48, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, 48, dst));
+ break;
case Iop_Sar32:
addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, dst));
addInstr(env, AMD64Instr_Sh64(Ash_SAR, 32, dst));
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