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From: <sv...@va...> - 2005-06-29 19:01:38
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Author: cerion
Date: 2005-06-29 20:01:32 +0100 (Wed, 29 Jun 2005)
New Revision: 1231
Log:
some more isel cases: v128,f32
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-29 18:53:23 UTC (rev 1230)
+++ trunk/priv/host-ppc32/isel.c 2005-06-29 19:01:32 UTC (rev 1231)
@@ -1353,7 +1353,7 @@
return r_dst;
}
=20
-//.. case Iop_128to32: {
+//.. case Iop_V128to32: {
//.. HReg dst =3D newVRegI(env);
//.. HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
@@ -2325,28 +2325,33 @@
return;
}
=20
-//.. /* 128{HI}to64 */
-//.. case Iop_128HIto64:
-//.. case Iop_128to64: {
-//.. Int off =3D e->Iex.Unop.op=3D=3DIop_128HIto64 ? 8 : 0;
-//.. HReg tLo =3D newVRegI(env);
-//.. HReg tHi =3D newVRegI(env);
-//.. HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. X86AMode* espLO =3D X86AMode_IR(off, hregX86_ESP());
-//.. X86AMode* espHI =3D X86AMode_IR(off+4, hregX86_ESP());
-//.. sub_from_esp(env, 16);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, esp=
0));
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV,=20
-//.. X86RMI_Mem(espLO), tLo )=
);
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV,=20
-//.. X86RMI_Mem(espHI), tHi )=
);
-//.. add_to_esp(env, 16);
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
+ /* V128{HI}to64 */
+ case Iop_V128HIto64:
+ case Iop_V128to64: {
+ Int off =3D e->Iex.Unop.op=3D=3DIop_V128HIto64 ? 0 : 8;
+ HReg tLo =3D newVRegI(env);
+ HReg tHi =3D newVRegI(env);
+ HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
+ PPC32AMode *sp0, *spLO, *spHI;
+
+ sub_from_sp( env, 32 ); // Move SP down 32 bytes
+ sp0 =3D PPC32AMode_IR(0, StackFramePtr);
+ spHI =3D PPC32AMode_IR(off, StackFramePtr);
+ spLO =3D PPC32AMode_IR(off+4, StackFramePtr);
+
+ // store as Vec128
+ addInstr(env, PPC32Instr_AvLdSt( False/*store*/, 16, vec, sp=
0 ));
+
+ // load hi,lo words (of hi/lo half of vec) as Ity_I32's
+ addInstr(env, PPC32Instr_Load( 4, False, tHi, spHI ));
+ addInstr(env, PPC32Instr_Load( 4, False, tLo, spLO ));
+
+ add_to_sp( env, 32 ); // Reset SP
+ *rHi =3D tHi;
+ *rLo =3D tLo;
+ return;
+ }
+
//.. /* could do better than this, but for now ... */
//.. case Iop_1Sto64: {
//.. HReg tLo =3D newVRegI(env);
@@ -2971,7 +2976,7 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_32Uto128: {
+//.. case Iop_32UtoV128: {
//.. HReg dst =3D newVRegV(env);
//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
//.. X86RMI* rmi =3D iselIntExpr_RMI(env, e->Iex.Unop.arg);
@@ -2981,7 +2986,7 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_64Uto128: {
+//.. case Iop_64UtoV128: {
//.. HReg rHi, rLo;
//.. HReg dst =3D newVRegV(env);
//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
@@ -3001,7 +3006,7 @@
//.. if (e->tag =3D=3D Iex_Binop) {
//.. switch (e->Iex.Binop.op) {
//..=20
-//.. case Iop_Set128lo32: {
+//.. case Iop_SetV128lo32: {
//.. HReg dst =3D newVRegV(env);
//.. HReg srcV =3D iselVecExpr(env, e->Iex.Binop.arg1);
//.. HReg srcI =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
@@ -3014,7 +3019,7 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_Set128lo64: {
+//.. case Iop_SetV128lo64: {
//.. HReg dst =3D newVRegV(env);
//.. HReg srcV =3D iselVecExpr(env, e->Iex.Binop.arg1);
//.. HReg srcIhi, srcIlo;
@@ -3030,7 +3035,7 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_64HLto128: {
+//.. case Iop_64HLtoV128: {
//.. HReg r3, r2, r1, r0;
//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
//.. X86AMode* esp4 =3D advance4(esp0);
@@ -3154,9 +3159,9 @@
//.. case Iop_InterleaveLO64x2:=20
//.. op =3D Xsse_UNPCKLQ; arg1isEReg =3D True; goto do_SseReRg;
//..=20
-//.. case Iop_And128: op =3D Xsse_AND; goto do_SseReRg;
-//.. case Iop_Or128: op =3D Xsse_OR; goto do_SseReRg;
-//.. case Iop_Xor128: op =3D Xsse_XOR; goto do_SseReRg;
+//.. case Iop_AndV128: op =3D Xsse_AND; goto do_SseReRg;
+//.. case Iop_OrV128: op =3D Xsse_OR; goto do_SseReRg;
+//.. case Iop_XorV128: op =3D Xsse_XOR; goto do_SseReRg;
//.. case Iop_Add8x16: op =3D Xsse_ADD8; goto do_SseReRg;
//.. case Iop_Add16x8: op =3D Xsse_ADD16; goto do_SseReRg;
//.. case Iop_Add32x4: op =3D Xsse_ADD32; goto do_SseReRg;
@@ -3327,6 +3332,12 @@
addInstr(env, PPC32Instr_Store( 4, am_addr4, rLo ));
return;
}
+//.. if (ty =3D=3D Ity_V128) {
+//.. HReg vec =3D iselVecExpr(env, stmt->Ist.Put.data);
+//.. X86AMode* am =3D X86AMode_IR(stmt->Ist.Put.offset, hregX8=
6_EBP());
+//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, am));
+//.. return;
+//.. }
//.. if (ty =3D=3D Ity_F32) {
//.. HReg f32 =3D iselFltExpr(env, stmt->Ist.Put.data);
//.. X86AMode* am =3D X86AMode_IR(stmt->Ist.Put.offset, hregX8=
6_EBP());
@@ -3402,18 +3413,18 @@
addInstr(env, PPC32Instr_FpUnary(Pfp_MOV, fr_dst, fr_src));
return;
}
-//.. if (ty =3D=3D Ity_F32) {
-//.. HReg dst =3D lookupIRTemp(env, tmp);
-//.. HReg src =3D iselFltExpr(env, stmt->Ist.Tmp.data);
-//.. addInstr(env, X86Instr_FpUnary(Xfp_MOV,src,dst));
-//.. return;
-//.. }
-//.. if (ty =3D=3D Ity_V128) {
-//.. HReg dst =3D lookupIRTemp(env, tmp);
-//.. HReg src =3D iselVecExpr(env, stmt->Ist.Tmp.data);
-//.. addInstr(env, mk_vMOVsd_RR(src,dst));
-//.. return;
-//.. }
+ if (ty =3D=3D Ity_F32) {
+ HReg fr_dst =3D lookupIRTemp(env, tmp);
+ HReg fr_src =3D iselFltExpr(env, stmt->Ist.Tmp.data);
+ addInstr(env, PPC32Instr_FpUnary(Pfp_MOV, fr_dst, fr_src));
+ return;
+ }
+ if (ty =3D=3D Ity_V128) {
+ HReg v_dst =3D lookupIRTemp(env, tmp);
+ HReg v_src =3D iselVecExpr(env, stmt->Ist.Tmp.data);
+ addInstr(env, PPC32Instr_AvUnary(Pav_MOV, v_dst, v_src));
+ return;
+ }
break;
}
=20
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