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From: <sv...@va...> - 2005-06-29 10:16:21
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Author: sewardj
Date: 2005-06-29 11:16:14 +0100 (Wed, 29 Jun 2005)
New Revision: 4052
Log:
ppc32: reinstate collection of cache-line-size info from the auxv
array at startup. This is used in m_transtab. However this info is
not yet fed to Vex, so it's still important to zero-out the auxv field
holding cache line size info passed to the client, so as to stop the
client's glibc using dcbz. This will be fixed.
Also get rid of a bunch more ppc32-specific vdso stuff in m_main that
doesn't need to be done. This now means ppc32-linux specifics in
m_main are only marginally intrusive than the x86-linux or amd64-linux
specifics in m_main.
Modified:
trunk/coregrind/m_machine.c
trunk/coregrind/m_main.c
trunk/coregrind/m_transtab.c
trunk/coregrind/pub_core_machine.h
Modified: trunk/coregrind/m_machine.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_machine.c 2005-06-29 08:46:30 UTC (rev 4051)
+++ trunk/coregrind/m_machine.c 2005-06-29 10:16:14 UTC (rev 4052)
@@ -196,6 +196,16 @@
return VG_INVALID_THREADID;
}
=20
+//////////////////////////////////////////////////////////////////
+// Architecture specifics
+
+// PPC: what is the cache line size (for dcbz etc) ?
+// This info is harvested on Linux at startup from the AT_SYSINFO
+// entries. 0 means not-yet-set.
+#if defined(VGA_ppc32)
+Int VG_(cache_line_size_ppc32) =3D 0;
+#endif
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c 2005-06-29 08:46:30 UTC (rev 4051)
+++ trunk/coregrind/m_main.c 2005-06-29 10:16:14 UTC (rev 4052)
@@ -122,13 +122,7 @@
static Int vg_argc;
static Char **vg_argv;
=20
-#if defined(VGP_ppc32_linux)
-/* From the aux vector */
-Int VG_(cache_line_size);
-UInt VG_(hardware_capabilities);
-#endif
=20
-
/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
/*=3D=3D=3D Counters, for profiling purposes only =
=3D=3D=3D*/
/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
@@ -173,28 +167,28 @@
found |=3D 2;
break;
=20
-#if defined(VGP_ppc32_linux)
+# if defined(VGP_ppc32_linux)
case AT_DCACHEBSIZE:
case AT_ICACHEBSIZE:
case AT_UCACHEBSIZE:
- VG_(debugLog)(1, "main", "PPC32 cache line size %u (type %u)\n"=
,=20
- (UInt)auxv->u.a_val, (UInt)auxv->a_type );
- if (auxv->u.a_val)
- VG_(cache_line_size) =3D auxv->u.a_val;
- // XXX: Nasty hack to stop use of badly implemented
- // cache-control instns in vex (dcbz)
- auxv->u.a_val =3D 0;
+ if (auxv->u.a_val > 0) {
+ VG_(cache_line_size_ppc32) =3D auxv->u.a_val;
+ VG_(debugLog)(1, "main",=20
+ "PPC32 cache line size %u (type %u)\n",=20
+ (UInt)auxv->u.a_val, (UInt)auxv->a_type );
+ }
+ /* HACK: Tell glibc we don't know what the line size is.
+ This stops it using dcbz. */
+ auxv->u.a_val =3D 0;
break;
+# endif
=20
- case AT_HWCAP:
- VG_(hardware_capabilities) =3D auxv->u.a_val;
- break;
-#endif
-
case AT_PHDR:
VG_(valgrind_base) =3D VG_PGROUNDDN(auxv->u.a_val);
break;
=20
+ default:
+ break;
}
=20
if ( found !=3D (1|2) ) {
Modified: trunk/coregrind/m_transtab.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_transtab.c 2005-06-29 08:46:30 UTC (rev 4051)
+++ trunk/coregrind/m_transtab.c 2005-06-29 10:16:14 UTC (rev 4052)
@@ -30,12 +30,13 @@
*/
=20
#include "pub_core_basics.h"
+#include "pub_core_machine.h" // ppc32: VG_(cache_line_size_ppc32)
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
-#include "pub_core_libcmman.h" // For VG_(get_memory_from_mmap)()
+#include "pub_core_libcmman.h" // For VG_(get_memory_from_mmap)()
#include "pub_core_libcprint.h"
#include "pub_core_options.h"
-#include "pub_core_tooliface.h" // For VG_(details).avg_translation_=
sizeB
+#include "pub_core_tooliface.h" // For VG_(details).avg_translation_siz=
eB
#include "pub_core_transtab.h"
=20
/* #define DEBUG_TRANSTAB */
@@ -324,14 +325,17 @@
invalidateFastCache();
}
=20
-#if defined(VGA_ppc32)
-static void invalidate_icache(void *ptr, int nbytes)
+static void invalidate_icache ( void *ptr, Int nbytes )
{
- unsigned long startaddr =3D (unsigned long) ptr;
- unsigned long endaddr =3D startaddr + nbytes;
- unsigned long addr;
- unsigned long cls =3D 16; //VG_(cache_line_size);
+# if defined(VGA_ppc32)
+ Addr startaddr =3D (Addr) ptr;
+ Addr endaddr =3D startaddr + nbytes;
+ Addr cls =3D VG_(cache_line_size_ppc32);
+ Addr addr;
=20
+ /* Surely no real cache would have a different line size? */
+ vg_assert(cls =3D=3D 16 || cls =3D=3D 32 || cls =3D=3D 64);
+
startaddr &=3D ~(cls - 1);
for (addr =3D startaddr; addr < endaddr; addr +=3D cls)
asm volatile("dcbst 0,%0" : : "r" (addr));
@@ -339,8 +343,17 @@
for (addr =3D startaddr; addr < endaddr; addr +=3D cls)
asm volatile("icbi 0,%0" : : "r" (addr));
asm volatile("sync; isync");
+
+# elif defined(VGA_x86)
+ /* no need to do anything, hardware provides coherence */
+
+# elif defined(VGA_amd64)
+ /* no need to do anything, hardware provides coherence */
+
+# else
+# error "Unknown ARCH"
+# endif
}
-#endif
=20
=20
/* Add a translation of vge to TT/TC. The translation is temporarily
@@ -421,9 +434,7 @@
sectors[y].tc_next +=3D reqdQ;
sectors[y].tt_n_inuse++;
=20
-#if defined(VGA_ppc32)
invalidate_icache( dstP, code_len );
-#endif
=20
/* more paranoia */
tce2 =3D sectors[y].tc_next;
Modified: trunk/coregrind/pub_core_machine.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_machine.h 2005-06-29 08:46:30 UTC (rev 4051)
+++ trunk/coregrind/pub_core_machine.h 2005-06-29 10:16:14 UTC (rev 4052)
@@ -88,6 +88,15 @@
// Offsets for the Vex state
#define VG_O_STACK_PTR (offsetof(VexGuestArchState, VG_STACK_PTR)=
)
=20
+// Architecture specifics
+
+// PPC: what is the cache line size (for dcbz etc) ?
+// This info is harvested on Linux at startup from the AT_SYSINFO
+// entries.
+#if defined(VGA_ppc32)
+extern Int VG_(cache_line_size_ppc32);
+#endif
+
#endif // __PUB_CORE_MACHINE_H
=20
/*--------------------------------------------------------------------*/
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