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From: <sv...@va...> - 2005-06-28 21:07:04
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Author: cerion
Date: 2005-06-28 22:07:02 +0100 (Tue, 28 Jun 2005)
New Revision: 1228
Log:
Implemented just enough of isel for an AltiVec store
- ls runs on g5 now, yay!
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-28 20:59:18 UTC (rev 1227)
+++ trunk/priv/host-ppc32/isel.c 2005-06-28 21:07:02 UTC (rev 1228)
@@ -54,12 +54,13 @@
GPR2 TOC pointer - not used
GPR3:12 Allocateable
GPR13 Thread-specific pointer - not used
- GPR14:30 Allocateable
+ GPR14:29 Allocateable
+ GPR30 AltiVec temp spill register
GPR31 GuestStatePointer
=20
Of Allocateable regs:
GPR3:12 Caller-saved regs
- GPR14:30 Callee-saved regs
+ GPR14:29 Callee-saved regs
=20
GPR3 [Return | Parameter] - carrying reg
GPR4:10 Parameter-carrying regs
@@ -218,12 +219,12 @@
return reg;
}
=20
-//.. static HReg newVRegV ( ISelEnv* env )
-//.. {
-//.. HReg reg =3D mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*=
/);
-//.. env->vreg_ctr++;
-//.. return reg;
-//.. }
+static HReg newVRegV ( ISelEnv* env )
+{
+ HReg reg =3D mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
+ env->vreg_ctr++;
+ return reg;
+}
=20
=20
/*---------------------------------------------------------*/
@@ -259,8 +260,8 @@
static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
=20
-//.. static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
-//.. static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
+static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
=20
=20
/*---------------------------------------------------------*/
@@ -2768,61 +2769,42 @@
}
=20
=20
-//.. /*---------------------------------------------------------*/
-//.. /*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
-//.. /*---------------------------------------------------------*/
-//..=20
-//.. static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
-//.. {
-//.. HReg r =3D iselVecExpr_wrk( env, e );
-//.. # if 0
-//.. vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
-//.. # endif
-//.. vassert(hregClass(r) =3D=3D HRcVec128);
-//.. vassert(hregIsVirtual(r));
-//.. return r;
-//.. }
-//..=20
-//..=20
-//.. /* DO NOT CALL THIS DIRECTLY */
-//.. static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
-//.. {
-//..=20
-/*
-//.. # define REQUIRE_SSE1 \
-//.. do { if (env->subarch =3D=3D VexSubArchX86_sse0) \
-//.. goto vec_fail; \
-//.. } while (0)
-//..=20
-//.. # define REQUIRE_SSE2 \
-//.. do { if (env->subarch =3D=3D VexSubArchX86_sse0 \
-//.. || env->subarch =3D=3D VexSubArchX86_sse1) \
-//.. goto vec_fail; \
-//.. } while (0)
-*/
+/*---------------------------------------------------------*/
+/*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
+/*---------------------------------------------------------*/
+
+static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
+{
+ HReg r =3D iselVecExpr_wrk( env, e );
+# if 0
+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
+# endif
+ vassert(hregClass(r) =3D=3D HRcVec128);
+ vassert(hregIsVirtual(r));
+ return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+{
//.. Bool arg1isEReg =3D False;
-//.. X86SseOp op =3D Xsse_INVALID;
-//.. IRType ty =3D typeOfIRExpr(env->type_env,e);
-//.. vassert(e);
-//.. vassert(ty =3D=3D Ity_V128);
-//..=20
-//.. REQUIRE_SSE1;
-//..=20
-//.. if (e->tag =3D=3D Iex_Tmp) {
-//.. return lookupIRTemp(env, e->Iex.Tmp.tmp);
-//.. }
-//..=20
-//.. if (e->tag =3D=3D Iex_Get) {
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, X86Instr_SseLdSt(
-//.. True/*load*/,=20
-//.. dst,
-//.. X86AMode_IR(e->Iex.Get.offset, hregX86_EBP()=
)
-//.. )
-//.. );
-//.. return dst;
-//.. }
-//..=20
+ PPC32AvOp op =3D Pav_INVALID;
+ IRType ty =3D typeOfIRExpr(env->type_env,e);
+ vassert(e);
+ vassert(ty =3D=3D Ity_V128);
+
+ if (e->tag =3D=3D Iex_Tmp) {
+ return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ }
+
+ if (e->tag =3D=3D Iex_Get) {
+ HReg dst =3D newVRegV(env);
+ addInstr(env,
+ PPC32Instr_AvLdSt( True/*load*/, 16, dst,
+ PPC32AMode_IR(e->Iex.Get.offset, Guest=
StatePtr)));
+ return dst;
+ }
+
//.. if (e->tag =3D=3D Iex_LDle) {
//.. HReg dst =3D newVRegV(env);
//.. X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
@@ -3261,18 +3243,15 @@
//.. addInstr(env, X86Instr_SseCMov(Xcc_Z,r0,dst));
//.. return dst;
//.. }
-//..=20
-//.. vec_fail:
-//.. vex_printf("iselVecExpr (subarch =3D %s): can't reduce\n",
-//.. LibVEX_ppVexSubArch(env->subarch));
-//.. ppIRExpr(e);
-//.. vpanic("iselVecExpr_wrk");
-//..=20
-//.. # undef REQUIRE_SSE1
-//.. # undef REQUIRE_SSE2
-//.. }
=20
+ vec_fail:
+ vex_printf("iselVecExpr(ppc32) (subarch =3D %s): can't reduce\n",
+ LibVEX_ppVexSubArch(env->subarch));
+ ppIRExpr(e);
+ vpanic("iselVecExpr_wrk(ppc32)");
+}
=20
+
/*---------------------------------------------------------*/
/*--- ISEL: Statements ---*/
/*---------------------------------------------------------*/
@@ -3320,11 +3299,11 @@
//.. Xalu_MOV, X86RI_Reg(vHi), X86AMode_IR(4, =
rA)));
//.. return;
//.. }
-//.. if (tyd =3D=3D Ity_V128) {
-//.. HReg r =3D iselVecExpr(env, stmt->Ist.STle.data);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, r, am));
-//.. return;
-//.. }
+ if (tyd =3D=3D Ity_V128) {
+ HReg v_src =3D iselVecExpr(env, stmt->Ist.STle.data);
+ addInstr(env, PPC32Instr_AvLdSt(False/*store*/, 16, v_src, am_a=
ddr));
+ return;
+ }
break;
}
=20
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