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From: <sv...@va...> - 2005-06-23 11:00:19
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Author: cerion
Date: 2005-06-23 12:00:14 +0100 (Thu, 23 Jun 2005)
New Revision: 1218
Log:
Added to insn selector: CmpNEZ8, Ist_Put::Ity_I64
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-23 08:44:52 UTC (rev 1217)
+++ trunk/priv/host-ppc32/isel.c 2005-06-23 11:00:14 UTC (rev 1218)
@@ -434,23 +434,25 @@
}
=20
=20
-//.. /* Given an amode, return one which references 4 bytes further
-//.. along. */
-//..=20
-//.. static X86AMode* advance4 ( X86AMode* am )
-//.. {
-//.. X86AMode* am4 =3D dopyX86AMode(am);
-//.. switch (am4->tag) {
-//.. case Xam_IRRS:
-//.. am4->Xam.IRRS.imm +=3D 4; break;
-//.. case Xam_IR:
-//.. am4->Xam.IR.imm +=3D 4; break;
-//.. default:
-//.. vpanic("advance4(x86,host)");
-//.. }
-//.. return am4;
-//.. }
+/* Given an amode, return one which references 4 bytes further
+ along. */
=20
+static PPC32AMode* advance4 ( ISelEnv* env, PPC32AMode* am )
+{
+ PPC32AMode* am4 =3D dopyPPC32AMode(am);
+ switch (am4->tag) {
+ case Pam_IR:
+ am4->Pam.RR.index +=3D 4; break;
+ case Pam_RR: {
+ HReg r_index =3D am4->Pam.IR.index;
+ addInstr(env, PPC32Instr_Alu32(Palu_ADD, r_index, r_index, PPC3=
2RI_Imm(4)));
+ break;
+ }
+ default:
+ vpanic("advance4(ppc32,host)");
+ }
+ return am4;
+}
=20
//.. /* Push an arg onto the host stack, in preparation for a call to a
//.. helper function of some kind. Returns the number of 32-bit word=
s
@@ -1598,7 +1600,7 @@
//.. return iselCondCode(env, expr1);
//.. }
=20
- /* pattern: 32to1(expr32) */
+ /* 32to1(expr32) */
DEFINE_PATTERN(p_32to1, unop(Iop_32to1,bind(0)));
if (matchIRExpr(&mi,p_32to1,e)) {
HReg r_dst =3D iselIntExpr_R(env, mi.bindee[0]);
@@ -1606,6 +1608,18 @@
return mk_PPCCondCode( Pct_TRUE, Pcf_EQ );
}
=20
+ /* --- patterns rooted at: CmpNEZ8 --- */
+
+ /* CmpNEZ8(x) */
+ if (e->tag =3D=3D Iex_Unop
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ8) {
+ HReg r_32 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_l =3D newVRegI(env);
+ addInstr(env, PPC32Instr_Alu32(Palu_AND, r_l, r_32, PPC32RI_Imm(0x=
FF)));
+ addInstr(env, PPC32Instr_Cmp32(Pcmp_S, 7, r_l, PPC32RI_Imm(0)));
+ return mk_PPCCondCode( Pct_FALSE, Pcf_EQ );
+ }
+
/* --- patterns rooted at: CmpNEZ32 --- */
=20
/* CmpNEZ32(x) */
@@ -3296,15 +3310,15 @@
addInstr(env, PPC32Instr_Store( sizeofIRType(ty), am_addr, r_sr=
c ));
return;
}
-//.. if (ty =3D=3D Ity_I64) {
-//.. HReg vHi, vLo;
-//.. X86AMode* am =3D X86AMode_IR(stmt->Ist.Put.offset, hregX8=
6_EBP());
-//.. X86AMode* am4 =3D advance4(am);
-//.. iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Put.data);
-//.. addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(vLo), a=
m ));
-//.. addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(vHi), a=
m4 ));
-//.. return;
-//.. }
+ if (ty =3D=3D Ity_I64) {
+ HReg rHi, rLo;
+ PPC32AMode* am_addr =3D PPC32AMode_IR(stmt->Ist.Put.offset, Gu=
estStatePtr);
+ PPC32AMode* am_addr4 =3D advance4(env, am_addr);
+ iselInt64Expr(&rHi,&rLo, env, stmt->Ist.Put.data);
+ addInstr(env, PPC32Instr_Store( 4, am_addr, rLo ));
+ addInstr(env, PPC32Instr_Store( 4, am_addr4, rHi ));
+ return;
+ }
//.. if (ty =3D=3D Ity_F32) {
//.. HReg f32 =3D iselFltExpr(env, stmt->Ist.Put.data);
//.. X86AMode* am =3D X86AMode_IR(stmt->Ist.Put.offset, hregX8=
6_EBP());
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