|
From: <sv...@va...> - 2005-06-20 12:42:24
|
Author: cerion
Date: 2005-06-20 13:42:04 +0100 (Mon, 20 Jun 2005)
New Revision: 1211
Log:
guest-ppc32
~~~~~~~~~~
- store-with-update instrs: Valgrind pagefault handler expects faulting a=
ddress >=3D current stack ptr, so we need to update the stack ptr registe=
r _before_ storing the old stack ptr
- branch_ctr_ok (bad calc for 'branch if %ctr zero' case)
- mcrf: scanning bitfields in the wrong direction
- on spotting the magic sequence, delta +=3D 24
- updated DIPs for +ve-only args
host-ppc32
~~~~~~~~~
- fixed CMov reg usage
- fixed Pin_Call in emit_PPC32Instr(): we already know how far we're jump=
ing
- fixed Pin_Goto in emit_PPC32Instr(): vassert right range of jump deltas
other-ppc32
~~~~~~~~~~
- exported OFFSET_ppc32_(various) for valgrind
Modified:
trunk/auxprogs/genoffsets.c
trunk/priv/guest-ppc32/gdefs.h
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
trunk/priv/host-ppc32/isel.c
trunk/pub/libvex_guest_ppc32.h
trunk/switchback/switchback.c
Modified: trunk/auxprogs/genoffsets.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/auxprogs/genoffsets.c 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/auxprogs/genoffsets.c 2005-06-20 12:42:04 UTC (rev 1211)
@@ -6,60 +6,98 @@
#include "../pub/libvex_basictypes.h"
#include "../pub/libvex_guest_x86.h"
#include "../pub/libvex_guest_amd64.h"
+#include "../pub/libvex_guest_ppc32.h"
=20
Int main ( void )
{
- printf("#define OFFSET_x86_EAX %d\n",=20
+ // x86
+ printf("#define OFFSET_x86_EAX %3d\n",=20
offsetof(VexGuestX86State,guest_EAX));
=20
- printf("#define OFFSET_x86_EBX %d\n",=20
+ printf("#define OFFSET_x86_EBX %3d\n",=20
offsetof(VexGuestX86State,guest_EBX));
=20
- printf("#define OFFSET_x86_ECX %d\n",=20
+ printf("#define OFFSET_x86_ECX %3d\n",=20
offsetof(VexGuestX86State,guest_ECX));
=20
- printf("#define OFFSET_x86_EDX %d\n",=20
+ printf("#define OFFSET_x86_EDX %3d\n",=20
offsetof(VexGuestX86State,guest_EDX));
=20
- printf("#define OFFSET_x86_ESI %d\n",=20
+ printf("#define OFFSET_x86_ESI %3d\n",=20
offsetof(VexGuestX86State,guest_ESI));
=20
- printf("#define OFFSET_x86_EDI %d\n",=20
+ printf("#define OFFSET_x86_EDI %3d\n",=20
offsetof(VexGuestX86State,guest_EDI));
=20
- printf("#define OFFSET_x86_EBP %d\n",=20
+ printf("#define OFFSET_x86_EBP %3d\n",=20
offsetof(VexGuestX86State,guest_EBP));
=20
- printf("#define OFFSET_x86_ESP %d\n",=20
+ printf("#define OFFSET_x86_ESP %3d\n",=20
offsetof(VexGuestX86State,guest_ESP));
=20
- printf("#define OFFSET_x86_EIP %d\n",=20
+ printf("#define OFFSET_x86_EIP %3d\n",=20
offsetof(VexGuestX86State,guest_EIP));
+ printf("\n");
=20
-
- printf("#define OFFSET_amd64_RAX %d\n",=20
+ // amd64
+ printf("#define OFFSET_amd64_RAX %3d\n",=20
offsetof(VexGuestAMD64State,guest_RAX));
=20
- printf("#define OFFSET_amd64_RDI %d\n",=20
+ printf("#define OFFSET_amd64_RDI %3d\n",=20
offsetof(VexGuestAMD64State,guest_RDI));
=20
- printf("#define OFFSET_amd64_RSI %d\n",=20
+ printf("#define OFFSET_amd64_RSI %3d\n",=20
offsetof(VexGuestAMD64State,guest_RSI));
=20
- printf("#define OFFSET_amd64_RDX %d\n",=20
+ printf("#define OFFSET_amd64_RDX %3d\n",=20
offsetof(VexGuestAMD64State,guest_RDX));
=20
- printf("#define OFFSET_amd64_R8 %d\n",=20
+ printf("#define OFFSET_amd64_R8 %3d\n",=20
offsetof(VexGuestAMD64State,guest_R8));
=20
- printf("#define OFFSET_amd64_R9 %d\n",=20
+ printf("#define OFFSET_amd64_R9 %3d\n",=20
offsetof(VexGuestAMD64State,guest_R9));
=20
- printf("#define OFFSET_amd64_R10 %d\n",=20
+ printf("#define OFFSET_amd64_R10 %3d\n",=20
offsetof(VexGuestAMD64State,guest_R10));
=20
- printf("#define OFFSET_amd64_RIP %d\n",=20
+ printf("#define OFFSET_amd64_RIP %3d\n",=20
offsetof(VexGuestAMD64State,guest_RIP));
=20
+ printf("\n");
+
+ // ppc32
+ printf("#define OFFSET_ppc32_GPR0 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR0));
+
+ printf("#define OFFSET_ppc32_GPR3 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR3));
+
+ printf("#define OFFSET_ppc32_GPR4 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR4));
+
+ printf("#define OFFSET_ppc32_GPR5 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR5));
+
+ printf("#define OFFSET_ppc32_GPR6 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR6));
+
+ printf("#define OFFSET_ppc32_GPR7 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR7));
+
+ printf("#define OFFSET_ppc32_GPR8 %3d\n",
+ offsetof(VexGuestPPC32State,guest_GPR8));
+
+ printf("#define OFFSET_ppc32_CIA %3d\n",
+ offsetof(VexGuestPPC32State,guest_CIA));
+
+ printf("#define OFFSET_ppc32_CC_OP %3d\n",
+ offsetof(VexGuestPPC32State,guest_CC_OP));
+
+ printf("#define OFFSET_ppc32_CC_DEP1 %3d\n",
+ offsetof(VexGuestPPC32State,guest_CC_DEP1));
+
+ printf("\n");
+
return 0;
}
Modified: trunk/priv/guest-ppc32/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/gdefs.h 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/priv/guest-ppc32/gdefs.h 2005-06-20 12:42:04 UTC (rev 1211)
@@ -41,7 +41,7 @@
=20
=20
/*---------------------------------------------------------*/
-/*--- ppc32 to IR conversion ---*/
+/*--- ppc32 to IR conversion ---*/
/*---------------------------------------------------------*/
=20
extern
@@ -75,7 +75,7 @@
/* --- CLEAN HELPERS --- */
=20
// Calculate CR7 flags
-extern UInt ppc32g_calculate_cr7_all ( UInt op, UInt val, UInt xer_so );
+extern UInt ppc32g_calculate_cr7 ( UInt op, UInt val, UInt xer_so );
=20
// Calculate XER flags
extern UInt ppc32g_calculate_xer_ov ( UInt op, UInt res, UInt argL, UIn=
t argR );
@@ -89,8 +89,9 @@
=20
The three words are:
=20
- CC_OP, which describes whether to return the DEP1 value as the fla=
gs,
- or to calculate the flags based on that value.
+ CC_OP, which describes whether to:
+ 0: Calculate the flags based on DEP1, DEP2.
+ 1: Return DEP1 as the flags.
=20
CC_DEP1: This holds either an immediate value to be returned as th=
e flags,
or a value with which to calculate the flags.
@@ -103,11 +104,11 @@
=20
A summary of the field usages is:
=20
- Operation DEP1 DEP2
+ Operation DEP1 DEP2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- 0 flags value unused
+ 0 calculation result xer_so
=20
- 1 result xer_so
+ 1 flags value unused
=20
*/
=20
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-06-20 12:42:04 UTC (rev 1211)
@@ -64,7 +64,7 @@
thunk parameters.
Returns values in high field (correct wrt actual CR)
*/
-UInt ppc32g_calculate_cr7_all ( UInt op, UInt val, UInt xer_so )
+UInt ppc32g_calculate_cr7 ( UInt op, UInt val, UInt xer_so )
{
if (op) { // val contains cr7 flags to be returned
return (val & 0xF0000000);
@@ -98,7 +98,7 @@
/* OV true if result can't be represented in 32 bits
i.e sHi !=3D sign extension of sLo */
Long l_res =3D (Long)((Int)argL) * (Long)((Int)argR);
- Int sHi =3D (Int)toUInt(l_res >> 32);
+ Int sHi =3D (Int)(l_res >> 32);
Int sLo =3D (Int)l_res;
return (sHi !=3D (sLo >> /*s*/ 31)) ? 1:0;
}
@@ -190,7 +190,7 @@
=20
/* VISIBLE TO LIBVEX CLIENT */
#if 0
-void LibVEX_GuestPPC32_put_flags ( UInt flags_native,
+void LibVEX_GuestPPC32_put_cr7 ( UInt flags_native,
/*OUT*/VexGuestPPC32State* vex_state )
{
vassert(0); // FIXME
@@ -198,9 +198,9 @@
#endif
=20
/* VISIBLE TO LIBVEX CLIENT */
-UInt LibVEX_GuestPPC32_get_flags ( /*IN*/VexGuestPPC32State* vex_state )
+UInt LibVEX_GuestPPC32_get_cr7 ( /*IN*/VexGuestPPC32State* vex_state )
{
- UInt flags =3D ppc32g_calculate_cr7_all(
+ UInt flags =3D ppc32g_calculate_cr7(
vex_state->guest_CC_OP,
vex_state->guest_CC_DEP1,
vex_state->guest_CC_DEP2
@@ -304,6 +304,8 @@
=20
.alwaysDefd=20
=3D { /* 0 */ ALWAYSDEFD(guest_CC_OP)
+
+ // FIXME
}
};
=20
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/priv/guest-ppc32/toIR.c 2005-06-20 12:42:04 UTC (rev 1211)
@@ -69,6 +69,10 @@
change during translation of a bb.=20
*/
=20
+/* We need to know this to do sub-register accesses correctly. */
+/* CONST */
+static Bool host_is_bigendian;
+
/* Pointer to the guest code area. */
/* CONST */
static UChar* guest_code;
@@ -302,13 +306,14 @@
vge->len[0] =3D 0;
=20
/* Set up globals. */
+ host_is_bigendian =3D host_bigendian;
guest_code =3D ppc32code;
guest_pc_bbstart =3D (Addr32)guest_pc_start;
irbb =3D emptyIRBB();
=20
vassert((guest_pc_start >> 32) =3D=3D 0);
=20
- /* Delta keeps track of how far along the x86code array we
+ /* Delta keeps track of how far along the ppc32code array we
have so far gone. */
delta =3D 0;
n_instrs =3D 0;
@@ -380,7 +385,7 @@
vassert(irbb->next =3D=3D NULL);
/* figure out a new delta to continue at. */
vassert(chase_into_ok(guest_next));
- delta =3D toUInt(guest_next - guest_pc_start);
+ delta =3D (UInt)(guest_next - guest_pc_start);
n_resteers++;
d_resteers++;
if (0 && (n_resteers & 0xFF) =3D=3D 0)
@@ -555,10 +560,12 @@
return IRExpr_Const(IRConst_U8(i));
}
=20
+#if 0
static IRExpr* mkU16 ( UShort i )
{
return IRExpr_Const(IRConst_U16(i));
}
+#endif
=20
static IRExpr* mkU32 ( UInt i )
{
@@ -602,7 +609,7 @@
/* -------------- Evaluating the flags-thunk. -------------- */
=20
/* Calculate CR7 (IBM CR0) conditional flags */
-static IRExpr* mk_ppc32g_calculate_cr7_all ( void )
+static IRExpr* mk_ppc32g_calculate_cr7 ( void )
{
IRExpr** args =3D
mkIRExprVec_3( IRExpr_Get(OFFB_CC_OP, Ity_I32),
@@ -612,7 +619,7 @@
=3D mkIRExprCCall(
Ity_I32,
0/*regparm*/,=20
- "ppc32g_calculate_cr7_all", &ppc32g_calculate_cr7_all,
+ "ppc32g_calculate_cr7", &ppc32g_calculate_cr7,
args
);
=20
@@ -682,7 +689,7 @@
flag-setting operation. Hence the various setFlags_* functions.
*/
=20
-/* Set the flags thunk OP=3D0, DEP1, DEP2 fields. */
+/* Set the flags thunk OP=3D0, DEP1, DEP2 fields. PPC32 p60 */
static void setFlags_CR7 ( IRExpr* result )
{
IRExpr* xer_so;
@@ -769,7 +776,8 @@
case PPC32_SPR_CR:
if (mask & 0xF0000000) {
// Call helper function to calculate latest CR7 from thunk:
- assign( val, binop(Iop_Or32, mk_ppc32g_calculate_cr7_all(),
+ // ... and OR it with CR0to6
+ assign( val, binop(Iop_Or32, mk_ppc32g_calculate_cr7(),
IRExpr_Get(OFFB_CR0to6, Ity_I32)) );
} else {
assign( val, IRExpr_Get(OFFB_CR0to6, Ity_I32) );
@@ -810,7 +818,7 @@
fld =3D getReg_masked( reg, (0xF << (field_idx*4)) );
=20
if (field_idx !=3D 0) {
- fld =3D binop(Iop_Shr32, fld, mkU8(toUChar(field_idx * 4)));
+ fld =3D binop(Iop_Shr32, fld, mkU8(field_idx * 4));
}
return fld;
}
@@ -826,7 +834,7 @@
val =3D getReg_masked( reg, 1<<bit_idx );
=20
if (bit_idx !=3D 0) {
- val =3D binop(Iop_Shr32, val, mkU8(toUChar(bit_idx)));
+ val =3D binop(Iop_Shr32, val, mkU8(bit_idx));
}
return val;
}
@@ -917,7 +925,7 @@
vassert( reg < PPC32_SPR_MAX );
=20
if (field_idx !=3D 0) {
- src =3D binop(Iop_Shl32, src, mkU8(toUChar(field_idx * 4)));
+ src =3D binop(Iop_Shl32, src, mkU8(field_idx * 4));
} =20
putReg_masked( reg, src, (0xF << (field_idx*4)) );
}
@@ -930,7 +938,7 @@
vassert( reg < PPC32_SPR_MAX );
=20
if (bit_idx !=3D 0) {
- src =3D binop(Iop_Shl32, src, mkU8(toUChar(bit_idx)));
+ src =3D binop(Iop_Shl32, src, mkU8(bit_idx));
} =20
putReg_masked( reg, src, (1<<bit_idx) );
}
@@ -1332,13 +1340,13 @@
switch (opc1) {
case 0x0B: // cmpi (Compare Immediate, PPC32 p368)
EXTS_SIMM =3D extend_s_16to32(SIMM_16);
- DIP("cmpi crf%d,%d,r%d,0x%x\n", crfD, flag_L, Ra_addr, EXTS_SIMM);
+ DIP("cmpi crf%d,%u,r%d,0x%x\n", crfD, flag_L, Ra_addr, EXTS_SIMM);
irx_cmp_lt =3D binop(Iop_CmpLT32S, mkexpr(Ra), mkU32(EXTS_SIMM));
irx_cmp_eq =3D binop(Iop_CmpEQ32, mkexpr(Ra), mkU32(EXTS_SIMM));
break;
=20
case 0x0A: // cmpli (Compare Logical Immediate, PPC32 p370)
- DIP("cmpli crf%d,%d,r%d,0x%x\n", crfD, flag_L, Ra_addr, UIMM_16);
+ DIP("cmpli crf%d,%u,r%d,0x%x\n", crfD, flag_L, Ra_addr, UIMM_16);
irx_cmp_lt =3D binop(Iop_CmpLT32U, mkexpr(Ra), mkU32(UIMM_16));
irx_cmp_eq =3D binop(Iop_CmpEQ32, mkexpr(Ra), mkU32(UIMM_16));
break;
@@ -1354,13 +1362,13 @@
=20
switch (opc2) {
case 0x000: // cmp (Compare, PPC32 p367)
- DIP("cmp crf%d,%d,r%d,r%d\n", crfD, flag_L,
+ DIP("cmp crf%d,%u,r%d,r%d\n", crfD, flag_L,
Ra_addr, Rb_addr);
irx_cmp_lt =3D binop(Iop_CmpLT32S, mkexpr(Ra), mkexpr(Rb));
break;
=20
case 0x020: // cmpl (Compare Logical, PPC32 p369)
- DIP("cmpl crf%d,%d,r%d,r%d\n", crfD, flag_L,
+ DIP("cmpl crf%d,%u,r%d,r%d\n", crfD, flag_L,
Ra_addr, Rb_addr);
irx_cmp_lt =3D binop(Iop_CmpLT32U, mkexpr(Ra), mkexpr(Rb));
break;
@@ -1604,7 +1612,7 @@
=20
switch (opc1) {
case 0x14: // rlwimi (Rotate Left Word Immediate then Mask Insert, PP=
C32 p500)
- DIP("rlwimi%s r%d,r%d,%d,%d,%d\n", flag_Rc ? "." : "",
+ DIP("rlwimi%s r%d,r%d,%d,%u,%u\n", flag_Rc ? "." : "",
Ra_addr, Rs_addr, sh_imm, MaskBegin, MaskEnd);
// Ra =3D (ROTL(Rs, Imm) & mask) | (Ra & ~mask);
assign( Ra, binop(Iop_Or32,
@@ -1614,7 +1622,7 @@
break;
=20
case 0x15: // rlwinm (Rotate Left Word Immediate then AND with Mask, =
PPC32 p501)
- DIP("rlwinm%s r%d,r%d,%d,%d,%d\n", flag_Rc ? "." : "",
+ DIP("rlwinm%s r%d,r%d,%d,%u,%u\n", flag_Rc ? "." : "",
Ra_addr, Rs_addr, sh_imm, MaskBegin, MaskEnd);
// Ra =3D ROTL(Rs, Imm) & mask
assign( Ra, binop(Iop_And32, ROTL32(mkexpr(Rs),
@@ -1622,7 +1630,7 @@
break;
=20
case 0x17: // rlwnm (Rotate Left Word then AND with Mask, PPC32 p503
- DIP("rlwnm%s r%d,r%d,r%d,%d,%d\n", flag_Rc ? "." : "",
+ DIP("rlwnm%s r%d,r%d,r%d,%u,%u\n", flag_Rc ? "." : "",
Ra_addr, Rs_addr, Rb_addr, MaskBegin, MaskEnd);
// Ra =3D ROTL(Rs, Rb[0-4]) & mask
assign( rot_amt,
@@ -1886,8 +1894,8 @@
return False;
}
DIP("stbu r%d,%d(r%d)\n", Rs_addr, (Int)d_imm, Ra_addr);
- storeBE( mkexpr(EA_imm), mkexpr(Rs_8) );
putIReg( Ra_addr, mkexpr(EA_imm) );
+ storeBE( mkexpr(EA_imm), mkexpr(Rs_8) );
break;
=20
case 0x2C: // sth (Store HW, PPC32 p522)
@@ -1901,9 +1909,8 @@
return False;
}
DIP("sthu r%d,%d(r%d)\n", Rs_addr, (Int)d_imm, Ra_addr);
- assign( Rs_16, binop(Iop_And16, mkexpr(Rs), mkU16(0xFFFF)) );
- storeBE( mkexpr(EA_imm), mkexpr(Rs_16) );
putIReg( Ra_addr, mkexpr(EA_imm) );
+ storeBE( mkexpr(EA_imm), mkexpr(Rs_16) );
break;
=20
case 0x24: // stw (Store W, PPC32 p530)
@@ -1917,8 +1924,8 @@
return False;
}
DIP("stwu r%d,%d(r%d)\n", Rs_addr, (Int)d_imm, Ra_addr);
- storeBE( mkexpr(EA_imm), mkexpr(Rs) );
putIReg( Ra_addr, mkexpr(EA_imm) );
+ storeBE( mkexpr(EA_imm), mkexpr(Rs) );
break;
=20
/* X Form */
@@ -1936,8 +1943,8 @@
return False;
}
DIP("stbux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
- storeBE( mkexpr(EA_reg), mkexpr(Rs_8) );
putIReg( Ra_addr, mkexpr(EA_reg) );
+ storeBE( mkexpr(EA_reg), mkexpr(Rs_8) );
break;
=20
case 0x0D7: // stbx (Store B Indexed, PPC32 p512)
@@ -1951,8 +1958,8 @@
return False;
}
DIP("sthux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
- storeBE( mkexpr(EA_reg), mkexpr(Rs_16) );
putIReg( Ra_addr, mkexpr(EA_reg) );
+ storeBE( mkexpr(EA_reg), mkexpr(Rs_16) );
break;
=20
case 0x197: // sthx (Store HW Indexed, PPC32 p526)
@@ -1966,8 +1973,8 @@
return False;
}
DIP("stwux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
- storeBE( mkexpr(EA_reg), mkexpr(Rs) );
putIReg( Ra_addr, mkexpr(EA_reg) );
+ storeBE( mkexpr(EA_reg), mkexpr(Rs) );
break;
=20
case 0x097: // stwx (Store W Indexed, PPC32 p536)
@@ -2104,7 +2111,7 @@
return False;
}
}
- DIP("lswi r%d,r%d,%d\n", Rd_addr, Ra_addr, NumBytes);
+ DIP("lswi r%d,r%d,%u\n", Rd_addr, Ra_addr, NumBytes);
=20
assign( EA, mkexpr(b_EA) );
=20
@@ -2135,7 +2142,7 @@
return False;
=20
case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528)
- DIP("stswi r%d,r%d,%d\n", Rs_addr, Ra_addr, NumBytes);
+ DIP("stswi r%d,r%d,%u\n", Rs_addr, Ra_addr, NumBytes);
if (Ra_addr =3D=3D 0) {
assign( EA, mkU32(0) );
} else {
@@ -2217,17 +2224,14 @@
static IRExpr* branch_ctr_ok( UInt BO )
{
IRTemp ok =3D newTemp(Ity_I1);
- IRTemp ctr_0 =3D newTemp(Ity_I1);
- =20
+
if ((BO >> 2) & 1) {
assign( ok, mkU1(1) );
} else {
- assign( ctr_0, unop(Iop_32to1, getReg_bit( PPC32_SPR_CTR, 0 )) );
-
if ((BO >> 1) & 1) {
- assign( ok, unop(Iop_Not1, mkexpr(ctr_0)) );
+ assign( ok, binop(Iop_CmpEQ32, getReg( PPC32_SPR_CTR ), mkU32(0=
)) );
} else {
- assign( ok, mkexpr(ctr_0) );
+ assign( ok, binop(Iop_CmpNE32, getReg( PPC32_SPR_CTR ), mkU32(0=
)) );
}
}
return mkexpr(ok);
@@ -2452,7 +2456,7 @@
=20
if (opc2 =3D=3D 0) { // mcrf (Move Cond Reg Field, PPC32 p464)
if (((crbD_addr & 0x3) !=3D 0) ||
- ((crbA_addr & 0x3) !=3D 0) || (crbB !=3D 0))
+ ((crbA_addr & 0x3) !=3D 0) || (crbB_addr !=3D 0))
return False;
DIP("mcrf crf%d,crf%d\n", crfD_addr, crfS_addr);
assign( tmp, getReg_field( PPC32_SPR_CR, (7-crfS_addr) ) );
@@ -2987,7 +2991,7 @@
DIP("mtcrf 0x%x,r%d\n", CRM, Rs_addr);
for (i=3D0; i<8; i++) {
if (CRM & (1<<i)) {
- mask =3D mask | (0xF << (7-i)*4);
+ mask |=3D (0xF << (i)*4);
}
}
putReg_masked( PPC32_SPR_CR, mkexpr(Rs), mask );
@@ -3856,6 +3860,7 @@
UInt* code =3D (UInt*)(guest_code + delta);
=20
/* Spot this: =20
+ 0x7C03D808 tw 0,3,27 =3D> trap word if(0) =3D> not=
hing
0x60000000 ori 0,0,0 =3D> r0 =3D r0 | 0
0x5400E800 rlwinm 0,0,29,0,0 =3D> r0 =3D rotl(r0,29)
0x54001800 rlwinm 0,0,3,0,0 =3D> r0 =3D rotl(r0,3)
@@ -3863,7 +3868,7 @@
0x54009800 rlwinm 0,0,19,0,0 =3D> r0 =3D rotl(r0,19)
0x60000000 ori 0,0,0 =3D> r0 =3D r0 | 0
*/
- if (code[0] =3D=3D 0x60000000 &&
+ if (code[0] =3D=3D 0x7C03D808 &&
code[1] =3D=3D 0x5400E800 &&
code[2] =3D=3D 0x54001800 &&
code[3] =3D=3D 0x54006800 &&
@@ -3874,7 +3879,8 @@
DIP("? =3D client_request ( ? )\n");
=20
*size =3D 24;
- =20
+ delta +=3D 24;
+
irbb->next =3D mkU32(guest_pc_bbstart+delta);
irbb->jumpkind =3D Ijk_ClientReq;
=20
@@ -3895,14 +3901,6 @@
#endif
=20
=20
- if (theInstr =3D=3D 0x7C0042A6) {
- // CAB: what's this?
- DIP("Invalid instruction! Would be 'mfspr 0,256', which doesn't ex=
ist!.\n");
- goto decode_failure;
-// DIP("Passing through for now...\n");
-// goto decode_success;
- }
-
// Note: all 'reserved' bits must be cleared, else invalid
switch (opc1) {
=20
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/priv/host-ppc32/hdefs.c 2005-06-20 12:42:04 UTC (rev 1211)
@@ -227,7 +227,7 @@
}
}
=20
-/* constructor */
+/* construct condition code */
PPC32CondCode mk_PPCCondCode ( PPC32CondTest test, PPC32CondFlag flag )
{
PPC32CondCode cc;
@@ -531,22 +531,6 @@
i->Pin.Div.srcR =3D srcR;
return i;
}
-//.. X86Instr* X86Instr_Sh3232 ( X86ShiftOp op, UInt amt, HReg src, HRe=
g dst ) {
-//.. X86Instr* i =3D LibVEX_Alloc(sizeof(X86Instr));
-//.. i->tag =3D Xin_Sh3232;
-//.. i->Xin.Sh3232.op =3D op;
-//.. i->Xin.Sh3232.amt =3D amt;
-//.. i->Xin.Sh3232.src =3D src;
-//.. i->Xin.Sh3232.dst =3D dst;
-//.. vassert(op =3D=3D Xsh_SHL || op =3D=3D Xsh_SHR);
-//.. return i;
-//.. }
-//.. X86Instr* X86Instr_Push( X86RMI* src ) {
-//.. X86Instr* i =3D LibVEX_Alloc(sizeof(X86Instr));
-//.. i->tag =3D Xin_Push;
-//.. i->Xin.Push.src =3D src;
-//.. return i;
-//.. }
PPC32Instr* PPC32Instr_Call ( PPC32CondCode cond, Addr32 target, Int reg=
parms ) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
i->tag =3D Pin_Call;
@@ -600,14 +584,6 @@
i->Pin.Set32.dst =3D dst;
return i;
}
-//.. X86Instr* X86Instr_Bsfr32 ( Bool isFwds, HReg src, HReg dst ) {
-//.. X86Instr* i =3D LibVEX_Alloc(sizeof(X86Instr));
-//.. i->tag =3D Xin_Bsfr32;
-//.. i->Xin.Bsfr32.isFwds =3D isFwds;
-//.. i->Xin.Bsfr32.src =3D src;
-//.. i->Xin.Bsfr32.dst =3D dst;
-//.. return i;
-//.. }
PPC32Instr* PPC32Instr_MFence ( void )
{
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
@@ -822,20 +798,6 @@
vex_printf(",");
ppHRegPPC32(i->Pin.Div.srcR);
return;
-//.. case Xin_Sh3232:
-//.. vex_printf("%sdl ", showX86ShiftOp(i->Xin.Sh3232.op));
-//.. if (i->Xin.Sh3232.amt =3D=3D 0)
-//.. vex_printf(" %%cl,");=20
-//.. else=20
-//.. vex_printf(" $%d,", i->Xin.Sh3232.amt);
-//.. ppHRegX86(i->Xin.Sh3232.src);
-//.. vex_printf(",");
-//.. ppHRegX86(i->Xin.Sh3232.dst);
-//.. return;
-//.. case Xin_Push:
-//.. vex_printf("pushl ");
-//.. ppX86RMI(i->Xin.Push.src);
-//.. return;
case Pin_Call:
vex_printf("call: ");
if (i->Pin.Call.cond.test !=3D Pct_ALWAYS) {
@@ -927,12 +889,6 @@
}
return;
}
-//.. case Xin_Bsfr32:
-//.. vex_printf("bs%cl ", i->Xin.Bsfr32.isFwds ? 'f' : 'r');
-//.. ppHRegX86(i->Xin.Bsfr32.src);
-//.. vex_printf(",");
-//.. ppHRegX86(i->Xin.Bsfr32.dst);
-//.. return;
case Pin_MFence:
vex_printf("mfence (=3Dsync)");
return;
@@ -1125,16 +1081,6 @@
addHRegUse(u, HRmRead, i->Pin.Div.srcL);
addHRegUse(u, HRmRead, i->Pin.Div.srcR);
return;
-//.. case Xin_Sh3232:
-//.. addHRegUse(u, HRmRead, i->Xin.Sh3232.src);
-//.. addHRegUse(u, HRmModify, i->Xin.Sh3232.dst);
-//.. if (i->Xin.Sh3232.amt =3D=3D 0)
-//.. addHRegUse(u, HRmRead, hregX86_ECX());
-//.. return;
-//.. case Xin_Push:
-//.. addRegUsage_X86RMI(u, i->Xin.Push.src);
-//.. addHRegUse(u, HRmModify, hregX86_ESP());
-//.. return;
case Pin_Call:
/* This is a bit subtle. */
/* First off, claim it trashes all the caller-saved regs
@@ -1183,7 +1129,7 @@
return;
case Pin_CMov32:
addRegUsage_PPC32RI(u, i->Pin.CMov32.src);
- addHRegUse(u, HRmModify, i->Pin.CMov32.dst);
+ addHRegUse(u, HRmWrite, i->Pin.CMov32.dst);
return;
case Pin_Load:
addRegUsage_PPC32AMode(u, i->Pin.Load.src);
@@ -1196,10 +1142,6 @@
case Pin_Set32:
addHRegUse(u, HRmWrite, i->Pin.Set32.dst);
return;
-//.. case Xin_Bsfr32:
-//.. addHRegUse(u, HRmRead, i->Xin.Bsfr32.src);
-//.. addHRegUse(u, HRmWrite, i->Xin.Bsfr32.dst);
-//.. return;
case Pin_MFence:
return;
//.. case Xin_FpUnary:
@@ -1364,13 +1306,6 @@
mapReg(m, &i->Pin.Div.srcL);
mapReg(m, &i->Pin.Div.srcR);
return;
-//.. case Xin_Sh3232:
-//.. mapReg(m, &i->Xin.Sh3232.src);
-//.. mapReg(m, &i->Xin.Sh3232.dst);
-//.. return;
-//.. case Xin_Push:
-//.. mapRegs_X86RMI(m, i->Xin.Push.src);
-//.. return;
case Pin_Call:
return;
case Pin_Goto:
@@ -1391,10 +1326,6 @@
case Pin_Set32:
mapReg(m, &i->Pin.Set32.dst);
return;
-//.. case Xin_Bsfr32:
-//.. mapReg(m, &i->Xin.Bsfr32.src);
-//.. mapReg(m, &i->Xin.Bsfr32.dst);
-//.. return;
case Pin_MFence:
return;
//.. case Xin_FpUnary:
@@ -1808,6 +1739,10 @@
//.. return p;
//.. }
=20
+/*
+ mkForm[...] refer to PPC32 instruction forms as per PPC32 p576
+*/
+
static UChar* mkFormD ( UChar* p, UInt opc1, UInt r1, UInt r2, UInt imm =
)
{
UInt theInstr;
@@ -1932,13 +1867,12 @@
return emit32(p, theInstr);
}
=20
-static UChar* doAMode_IR ( UChar* p, UInt opc1, HReg hrSD, PPC32AMode* a=
m )
+static UChar* doAMode_IR ( UChar* p, UInt opc1, UInt rSD, PPC32AMode* am=
)
{
- UInt rSD, rA, idx;
+ UInt rA, idx;
vassert(am->tag =3D=3D Pam_IR);
vassert(am->Pam.IR.index < 0x10000);
=20
- rSD =3D iregNo(hrSD);
rA =3D iregNo(am->Pam.IR.base);
idx =3D am->Pam.IR.index;
=20
@@ -1948,13 +1882,11 @@
=20
=20
static UChar* doAMode_RR ( UChar* p, UInt opc1, UInt opc2,
- HReg hrSD, PPC32AMode* am )
+ UInt rSD, PPC32AMode* am )
{
- UInt rSD, rA, rB;
-// vassert(hregClass(hrSD) =3D=3D HRcInt32); // CAB: etc. worth doing =
this?
+ UInt rA, rB;
vassert(am->tag =3D=3D Pam_RR);
=20
- rSD =3D iregNo(hrSD);
rA =3D iregNo(am->Pam.RR.base);
rB =3D iregNo(am->Pam.RR.index);
=20
@@ -2001,16 +1933,10 @@
Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i )
{
//.. UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, s=
ubopc;
-//..=20
-//.. UInt xtra;
+
UChar* p =3D &buf[0];
UChar* ptmp =3D p;
vassert(nbuf >=3D 32);
-//..=20
-//.. /* Wrap an integer as a int register, for use assembling
-//.. GrpN insns, in which the greg field is used as a sub-opcode
-//.. and does not really contain a register. */
-//.. # define fake(_n) mkHReg((_n), HRcInt32, False)
=20
// vex_printf("asm ");ppPPC32Instr(i); vex_printf("\n");
=20
@@ -2039,7 +1965,7 @@
} else {
p =3D mkFormX(p, opc1, r_srcL, r_dst, r_srcR, opc2, 0);
}
- } else { // Pri_Imm:
+ } else { // tag =3D=3D Pri_Imm:
imm_srcR =3D i->Pin.Alu32.srcR->Pri.Imm.imm32;
switch (i->Pin.Alu32.op) {
case Palu_ADD: opc1 =3D 14; break;
@@ -2215,50 +2141,18 @@
goto done;
}
=20
-//.. case Xin_Sh3232:
-//.. vassert(i->Xin.Sh3232.op =3D=3D Xsh_SHL || i->Xin.Sh3232.op =3D=
=3D Xsh_SHR);
-//.. if (i->Xin.Sh3232.amt =3D=3D 0) {
-//.. /* shldl/shrdl by %cl */
-//.. *p++ =3D 0x0F;
-//.. if (i->Xin.Sh3232.op =3D=3D Xsh_SHL) {
-//.. *p++ =3D 0xA5;
-//.. } else {
-//.. *p++ =3D 0xAD;
-//.. }
-//.. p =3D doAMode_R(p, i->Xin.Sh3232.src, i->Xin.Sh3232.dst);
-//.. goto done;
-//.. }
-//.. break;
-
-//.. case Xin_Push:
-//.. switch (i->Xin.Push.src->tag) {
-//.. case Xrmi_Mem:=20
-//.. *p++ =3D 0xFF;
-//.. p =3D doAMode_M(p, fake(6), i->Xin.Push.src->Xrmi.Mem.a=
m);
-//.. goto done;
-//.. case Xrmi_Imm:
-//.. *p++ =3D 0x68;
-//.. p =3D emit32(p, i->Xin.Push.src->Xrmi.Imm.imm32);
-//.. goto done;
-//.. case Xrmi_Reg:
-//.. *p++ =3D 0x50 + iregNo(i->Xin.Push.src->Xrmi.Reg.reg);
-//.. goto done;
-//.. default:=20
-//.. goto bad;
-//.. }
-
case Pin_Call: {
PPC32CondCode cond =3D i->Pin.Call.cond;
UInt r_dst =3D 12;
/* As per detailed comment for Pin_Call in
getRegUsage_PPC32Instr above, %r12 is used as an address temp *=
/
=20
- /* jump over the following two insns if condition does not hold */
+ /* jump over the following insns if condition does not hold */
if (cond.test !=3D Pct_ALWAYS) {
- /* don't know how many bytes to jump over yet...
- make space for a jump instruction and fill in later. */
- ptmp =3D p; /* fill in this bit later */
- p +=3D 4;
+ UInt delta =3D 4*4; /* jump 4 instrs */
+
+ /* bca !ct,cf,dst */
+ p =3D mkFormB(ptmp, invertCondTest(cond.test), cond.flag, (delt=
a>>2), 1, 0);
}
=20
/* load target to r_dst */
@@ -2269,15 +2163,6 @@
=20
/* bctrl =3D> branch to count register (and save to lr) */
p =3D mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1);
-
- /* Fix up the conditional jump, if there was one. */
- if (cond.test !=3D Pct_ALWAYS) {
- Int delta =3D p - ptmp;
- vassert(delta >=3D 8 && delta <=3D 16);
-
- /* bca !ct,cf,jump */
- mkFormB(ptmp, invertCondTest(cond.test), cond.flag, (delta>>2),=
1, 0);
- }
goto done;
}
=20
@@ -2319,26 +2204,26 @@
if (magic_num !=3D0) {
vassert(magic_num < 0x10000);
/* addi r31,0,magic_num */
- p =3D mkFormD(p, 14, 31, 0, magic_num);
+ p =3D mkFormD(p, 14, 31, 0, magic_num); // p +=3D 4
}
=20
/* Get the destination address into %r_return */
if (i->Pin.Goto.dst->tag =3D=3D Pri_Imm) {
imm_dst =3D i->Pin.Goto.dst->Pri.Imm.imm32;
- p =3D mkLoadImm(p, r_return, imm_dst);
+ p =3D mkLoadImm(p, r_return, imm_dst); // p +=3D 4|8
} else {
vassert(i->Pin.Goto.dst->tag =3D=3D Pri_Reg);
r_dst =3D iregNo(i->Pin.Goto.dst->Pri.Reg.reg);
- p =3D mkMoveReg(p, r_return, r_dst);
+ p =3D mkMoveReg(p, r_return, r_dst); // p +=3D 4
}
=20
/* blr */
- p =3D mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 16, 0);
+ p =3D mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 16, 0); // p +=3D 4
=20
/* Fix up the conditional jump, if there was one. */
if (cond.test !=3D Pct_ALWAYS) {
Int delta =3D p - ptmp;
- vassert(delta >=3D 8 && delta <=3D 16);
+ vassert(delta >=3D 12 && delta <=3D 20);
/* bc !ct,cf,delta */
mkFormB(ptmp, invertCondTest(cond.test), cond.flag, (delta>>2),=
0, 0);
}
@@ -2385,6 +2270,8 @@
}
=20
case Pin_Load: {
+ PPC32AMode* am_addr =3D i->Pin.Load.src;
+ UInt r_dst =3D iregNo(i->Pin.Load.dst);
Bool syned =3D i->Pin.Load.syned;
UInt opc1, opc2, sz =3D i->Pin.Load.sz;
switch (i->Pin.Load.src->tag) {
@@ -2395,17 +2282,16 @@
vassert(syned =3D=3D False);
opc1 =3D (sz =3D=3D 1) ? 34 : 32; // 1:4
}
- p =3D doAMode_IR(p, opc1, i->Pin.Load.dst, i->Pin.Load.src);
+ p =3D doAMode_IR(p, opc1, r_dst, am_addr);
goto done;
case Pam_RR:
- opc1 =3D 31;
if (sz =3D=3D 2) { // the only signed load
opc2 =3D (syned) ? 343: 279;
} else {
vassert(syned =3D=3D False);
opc2 =3D (sz =3D=3D 1) ? 87 : 23; // 1:4
}
- p =3D doAMode_RR(p, opc1, opc2, i->Pin.Load.dst, i->Pin.Load.sr=
c);
+ p =3D doAMode_RR(p, 31, opc2, r_dst, am_addr);
goto done;
default:
goto bad;
@@ -2442,37 +2328,25 @@
goto done;
}
=20
-//.. case Xin_Bsfr32:
-//.. *p++ =3D 0x0F;
-//.. if (i->Xin.Bsfr32.isFwds) {
-//.. *p++ =3D 0xBC;
-//.. } else {
-//.. *p++ =3D 0xBD;
-//.. }
-//.. p =3D doAMode_R(p, i->Xin.Bsfr32.dst, i->Xin.Bsfr32.src);
-//.. goto done;
-
case Pin_MFence: {
-// CAB: choose...
-#if 1 // sync (Synchronise, p616)
- p =3D mkFormX(p, 31, 0, 0, 0, 598, 0);
-#else // isync (instruction synchronise, p467)
- p =3D mkFormXL(p, 19, 0, 0, 0, 150, 0);
-#endif
+ p =3D mkFormX(p, 31, 0, 0, 0, 598, 0); // sync, PPC32 p616
+// CAB: Should this be isync?
+// p =3D mkFormXL(p, 19, 0, 0, 0, 150, 0); // isync, PPC32 p467
goto done;
}
=20
case Pin_Store: {
+ PPC32AMode* am_addr =3D i->Pin.Store.dst;
+ UInt r_src =3D iregNo(i->Pin.Store.src);
UInt opc1, opc2, sz =3D i->Pin.Store.sz;
switch (i->Pin.Store.dst->tag) {
case Pam_IR:
opc1 =3D (sz =3D=3D 1) ? 38 : ((sz =3D=3D 2) ? 44 : 36); /=
/ 1:2:4
- p =3D doAMode_IR(p, opc1, i->Pin.Store.src, i->Pin.Store.dst);
+ p =3D doAMode_IR(p, opc1, r_src, am_addr);
goto done;
case Pam_RR:
- opc1 =3D 31;
opc2 =3D (sz =3D=3D 1) ? 215 : ((sz =3D=3D 2) ? 407 : 151); /=
/ 1:2:4
- p =3D doAMode_RR(p, opc1, opc2, i->Pin.Store.src, i->Pin.Store.=
dst);
+ p =3D doAMode_RR(p, 31, opc2, r_src, am_addr);
goto done;
default:
goto bad;
@@ -2916,8 +2790,6 @@
done:
vassert(p - &buf[0] <=3D 32);
return p - &buf[0];
-
-# undef fake
}
=20
/*---------------------------------------------------------------*/
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/priv/host-ppc32/hdefs.h 2005-06-20 12:42:04 UTC (rev 1211)
@@ -48,7 +48,7 @@
=20
extern void ppHRegPPC32 ( HReg );
=20
-extern HReg hregPPC32_GPR0 ( void ); // reserved
+extern HReg hregPPC32_GPR0 ( void ); // scratch reg / zero reg
extern HReg hregPPC32_GPR1 ( void ); // Stack Frame Pointer
extern HReg hregPPC32_GPR2 ( void ); // TOC pointer - not used
extern HReg hregPPC32_GPR3 ( void );
@@ -297,23 +297,20 @@
/* --------- */
typedef
enum {
- Pin_Alu32, /* 32-bit mov/arith/logical */
- Pin_Sub32, /* 32-bit mov/arith/logical */
- Pin_Sh32, /* 32-bit shift/rotate */
- Pin_Cmp32, /* 32-bit compare */
- Pin_Unary32, /* 32-bit not, neg, clz */
- Pin_MulL, /* widening multiply */
- Pin_Div, /* div */
-//.. Xin_Sh3232, /* shldl or shrdl */
-//.. Xin_Push, /* push (32-bit?) value on stack */
- Pin_Call, /* call to address in register */
- Pin_Goto, /* conditional/unconditional jmp to dst */
- Pin_CMov32, /* conditional move */
- Pin_Load, /* load a 8|16|32 bit value from mem */
- Pin_Store, /* store a 8|16|32 bit value to mem */
- Pin_Set32, /* convert condition code to 32-bit value */
-//.. Xin_Bsfr32, /* 32-bit bsf/bsr */
- Pin_MFence, /* mem fence (not just sse2, but sse0 and 1 too) */
+ Pin_Alu32, /* 32-bit mov/arith/logical */
+ Pin_Sub32, /* 32-bit mov/arith/logical */
+ Pin_Sh32, /* 32-bit shift/rotate */
+ Pin_Cmp32, /* 32-bit compare */
+ Pin_Unary32, /* 32-bit not, neg, clz */
+ Pin_MulL, /* widening multiply */
+ Pin_Div, /* div */
+ Pin_Call, /* call to address in register */
+ Pin_Goto, /* conditional/unconditional jmp to dst */
+ Pin_CMov32, /* conditional move */
+ Pin_Load, /* load a 8|16|32 bit value from mem */
+ Pin_Store, /* store a 8|16|32 bit value to mem */
+ Pin_Set32, /* convert condition code to 32-bit value */
+ Pin_MFence, /* mem fence (not just sse2, but sse0 and 1 too) *=
/
=20
//.. Xin_FpUnary, /* FP fake unary op */
//.. Xin_FpBinary, /* FP fake binary op */
@@ -325,7 +322,7 @@
//.. Xin_FpStSW_AX, /* fstsw %ax */
//.. Xin_FpCmp, /* FP compare, generating a C320 value into in=
t reg */
=20
- Pin_RdWrLR /* Read/Write Link Register */
+ Pin_RdWrLR /* Read/Write Link Register */
}
PPC32InstrTag;
=20
@@ -378,16 +375,6 @@
HReg srcL;
HReg srcR;
} Div;
-//.. /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */
-//.. struct {
-//.. X86ShiftOp op;
-//.. UInt amt; /* shift amount, or 0 means %cl */
-//.. HReg src;
-//.. HReg dst;
-//.. } Sh3232;
-//.. struct {
-//.. X86RMI* src;
-//.. } Push;
/* Pseudo-insn. Call target (an absolute address), on given
condition (which could be Pct_ALWAYS). */
struct {
@@ -430,12 +417,6 @@
PPC32CondCode cond;
HReg dst;
} Set32;
-//.. /* 32-bit bsf or bsr. */
-//.. struct {
-//.. Bool isFwds;
-//.. HReg src;
-//.. HReg dst;
-//.. } Bsfr32;
/* Mem fence. In short, an insn which flushes all preceding
loads and stores as much as possible before continuing.
On PPC32 we emit a "sync". */
@@ -511,25 +492,22 @@
PPC32Instr;
=20
=20
-extern PPC32Instr* PPC32Instr_Alu32 ( PPC32AluOp, HReg, HReg, PPC32R=
I* );
-extern PPC32Instr* PPC32Instr_Sub32 ( HReg, PPC32RI*, HReg );
-extern PPC32Instr* PPC32Instr_Sh32 ( PPC32ShiftOp, HReg, HReg, PPC3=
2RI* );
-extern PPC32Instr* PPC32Instr_Cmp32 ( PPC32CmpOp, UInt, HReg, PPC32R=
I* );
-extern PPC32Instr* PPC32Instr_Unary32 ( PPC32UnaryOp op, HReg dst, HRe=
g src );
-extern PPC32Instr* PPC32Instr_MulL ( Bool syned, Bool word, HReg, H=
Reg, PPC32RI* );
-extern PPC32Instr* PPC32Instr_Div ( Bool syned, HReg dst, HReg src=
L, HReg srcR );
-//.. extern X86Instr* X86Instr_Sh3232 ( X86ShiftOp, UInt amt, HReg sr=
c, HReg dst );
-//.. extern X86Instr* X86Instr_Push ( X86RMI* );
-extern PPC32Instr* PPC32Instr_Call ( PPC32CondCode, Addr32, Int );
-extern PPC32Instr* PPC32Instr_Goto ( IRJumpKind, PPC32CondCode cond=
, PPC32RI* dst );
-extern PPC32Instr* PPC32Instr_CMov32 ( PPC32CondCode, HReg dst, PPC32=
RI* src );
-extern PPC32Instr* PPC32Instr_Load ( UChar sz, Bool syned,
- HReg dst, PPC32AMode* src );
-extern PPC32Instr* PPC32Instr_Store ( UChar sz, PPC32AMode* dst, HRe=
g src );
-extern PPC32Instr* PPC32Instr_Set32 ( PPC32CondCode cond, HReg dst )=
;
-//.. extern X86Instr* X86Instr_Bsfr32 ( Bool isFwds, HReg src, HReg d=
st );
-extern PPC32Instr* PPC32Instr_MFence ( void );
-//..=20
+extern PPC32Instr* PPC32Instr_Alu32 ( PPC32AluOp, HReg, HReg, PPC32=
RI* );
+extern PPC32Instr* PPC32Instr_Sub32 ( HReg, PPC32RI*, HReg );
+extern PPC32Instr* PPC32Instr_Sh32 ( PPC32ShiftOp, HReg, HReg, PPC=
32RI* );
+extern PPC32Instr* PPC32Instr_Cmp32 ( PPC32CmpOp, UInt, HReg, PPC32=
RI* );
+extern PPC32Instr* PPC32Instr_Unary32 ( PPC32UnaryOp op, HReg dst, HR=
eg src );
+extern PPC32Instr* PPC32Instr_MulL ( Bool syned, Bool word, HReg, =
HReg, PPC32RI* );
+extern PPC32Instr* PPC32Instr_Div ( Bool syned, HReg dst, HReg sr=
cL, HReg srcR );
+extern PPC32Instr* PPC32Instr_Call ( PPC32CondCode, Addr32, Int );
+extern PPC32Instr* PPC32Instr_Goto ( IRJumpKind, PPC32CondCode con=
d, PPC32RI* dst );
+extern PPC32Instr* PPC32Instr_CMov32 ( PPC32CondCode, HReg dst, PPC3=
2RI* src );
+extern PPC32Instr* PPC32Instr_Load ( UChar sz, Bool syned,
+ HReg dst, PPC32AMode* src );
+extern PPC32Instr* PPC32Instr_Store ( UChar sz, PPC32AMode* dst, HR=
eg src );
+extern PPC32Instr* PPC32Instr_Set32 ( PPC32CondCode cond, HReg dst =
);
+extern PPC32Instr* PPC32Instr_MFence ( void );
+
//.. extern X86Instr* X86Instr_FpUnary ( X86FpOp op, HReg src, HReg ds=
t );
//.. extern X86Instr* X86Instr_FpBinary ( X86FpOp op, HReg srcL, HReg s=
rcR, HReg dst );
//.. extern X86Instr* X86Instr_FpLdSt ( Bool isLoad, UChar sz, HReg r=
eg, X86AMode* );
@@ -540,7 +518,7 @@
//.. extern X86Instr* X86Instr_FpStSW_AX ( void );
//.. extern X86Instr* X86Instr_FpCmp ( HReg srcL, HReg srcR, HReg ds=
t );
=20
-extern PPC32Instr* PPC32Instr_RdWrLR ( Bool wrLR, HReg gpr );
+extern PPC32Instr* PPC32Instr_RdWrLR ( Bool wrLR, HReg gpr );
=20
=20
extern void ppPPC32Instr ( PPC32Instr* );
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/priv/host-ppc32/isel.c 2005-06-20 12:42:04 UTC (rev 1211)
@@ -342,7 +342,7 @@
return PPC32Instr_Alu32(Palu_ADD, r_dst, zero, PPC32RI_Imm(imm =
& 0xFFFF));
}
if (imm > 0xFFFF) {
- // CAB: addis (aka lis) would be good...
+ // CAB: perhaps add Palu_ADDIS ?
addInstr(env, PPC32Instr_Alu32(Palu_ADD, r_dst, zero, PPC32RI_I=
mm(imm>>16)));
addInstr(env, mk_sh32(env, Psh_SHL, r_dst, r_dst, PPC32RI_Imm(1=
6)));
return PPC32Instr_Alu32(Palu_OR, r_dst, r_dst, PPC32RI_Imm(imm =
& 0xFFFF));
@@ -351,7 +351,7 @@
addInstr(env, PPC32Instr_Alu32(Palu_ADD, r_dst, zero, PPC32RI_Imm(=
0)));
return PPC32Instr_Alu32(Palu_OR, r_dst, r_dst, ri_src);
} else {
- // mr rD,rS
+ // Just mr rD,rS
return PPC32Instr_Alu32(Palu_OR, r_dst, ri_src->Pri.Reg.reg, ri_sr=
c);
}
}
@@ -659,7 +659,7 @@
=20
/* Finally, the call itself. */
addInstr(env, PPC32Instr_Call( cc,
- toUInt(Ptr_to_ULong(cee->addr)),
+ Ptr_to_ULong(cee->addr),
n_args + (passBBP ? 1 : 0) ));
}
=20
@@ -835,9 +835,9 @@
/* --------- LOAD --------- */
case Iex_LDle: {
HReg r_dst =3D newVRegI(env);
- PPC32AMode* am_src =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ PPC32AMode* am_addr =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
- addInstr(env, PPC32Instr_Load( sizeofIRType(ty), False, r_dst, =
am_src ));
+ addInstr(env, PPC32Instr_Load( sizeofIRType(ty), False, r_dst, =
am_addr ));
return r_dst;
}
break;
@@ -1114,7 +1114,7 @@
//.. addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0x4700)=
, dst));
//.. return dst;
//.. }
-//..=20
+
break;
}
=20
@@ -1259,6 +1259,14 @@
addInstr(env, PPC32Instr_Unary32(Pun_CLZ,r_dst,r_src));
return r_dst;
}
+ case Iop_Neg8:
+ case Iop_Neg16:
+ case Iop_Neg32: {
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, PPC32Instr_Unary32(Pun_NEG,r_dst,r_src));
+ return r_dst;
+ }
=20
//.. case Iop_128to32: {
//.. HReg dst =3D newVRegI(env);
@@ -1287,8 +1295,8 @@
case Iex_Get: {
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
HReg r_dst =3D newVRegI(env);
- PPC32AMode* am_src =3D PPC32AMode_IR(e->Iex.Get.offset, GuestSt=
atePtr );
- addInstr(env, PPC32Instr_Load( sizeofIRType(ty), False, r_dst, =
am_src ));
+ PPC32AMode* am_addr =3D PPC32AMode_IR(e->Iex.Get.offset, GuestS=
tatePtr );
+ addInstr(env, PPC32Instr_Load( sizeofIRType(ty), False, r_dst, =
am_addr ));
return r_dst;
}
break;
@@ -1337,16 +1345,14 @@
case Iex_Mux0X: {
if ((ty =3D=3D Ity_I32 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I8)
&& typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) =3D=3D Ity_I8=
) {
- PPC32CondCode cc;
- HReg r_cond;
- HReg rX =3D iselIntExpr_R(env, e->Iex.Mux0X.exprX);
- PPC32RI* r0 =3D iselIntExpr_RI(env, e->Iex.Mux0X.expr0);
- HReg r_dst =3D newVRegI(env);
+ PPC32CondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_EQ );
+ HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg rX =3D iselIntExpr_R(env, e->Iex.Mux0X.exprX);
+ PPC32RI* r0 =3D iselIntExpr_RI(env, e->Iex.Mux0X.expr0);
+ HReg r_dst =3D newVRegI(env);
=20
addInstr(env, mk_iMOVds_RR(r_dst,rX));
- r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
addInstr(env, PPC32Instr_Cmp32(Pcmp_U, 7, r_cond, PPC32RI_Imm(0=
)));
- cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_EQ );
addInstr(env, PPC32Instr_CMov32(cc,r_dst,r0));
return r_dst;
}
@@ -1357,10 +1363,11 @@
break;
} /* switch (e->tag) */
=20
+
/* We get here if no pattern matched. */
irreducible:
ppIRExpr(e);
- vpanic("iselIntExpr_R: cannot reduce tree");
+ vpanic("iselIntExpr_R(ppc32): cannot reduce tree");
}
=20
=20
@@ -1520,6 +1527,8 @@
return cond;
}
=20
+ /* --- patterns rooted at: 32to1 --- */
+
//.. /* 32to1(1Uto32(expr1)) -- the casts are pointless, ignore them =
*/
//.. DEFINE_PATTERN(p_1Uto32_then_32to1,
//.. unop(Iop_32to1,unop(Iop_1Uto32,bind(0))));
@@ -1544,6 +1553,18 @@
return mk_PPCCondCode( Pct_TRUE, Pcf_EQ );
}
=20
+ /* --- patterns rooted at: CmpNEZ32 --- */
+
+ /* CmpNEZ32(x) */
+ if (e->tag =3D=3D Iex_Unop
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ32) {
+ HReg r1 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, PPC32Instr_Cmp32(Pcmp_S, 7, r1, PPC32RI_Imm(0)));
+ return mk_PPCCondCode( Pct_FALSE, Pcf_EQ );
+ }
+
+ /* --- patterns rooted at: Cmp{EQ,NE}{8,16} --- */
+
//.. /* CmpEQ8 / CmpNE8 */
//.. if (e->tag =3D=3D Iex_Binop=20
//.. && (e->Iex.Binop.op =3D=3D Iop_CmpEQ8
@@ -1884,14 +1905,14 @@
//.. *rLo =3D tLo;
//.. return;
//.. }
-//..=20
-//..=20
-//.. /* 32HLto64(e1,e2) */
-//.. case Iop_32HLto64:
-//.. *rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. *rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. return;
-//..=20
+
+
+ /* 32HLto64(e1,e2) */
+ case Iop_32HLto64:
+ *rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ *rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ return;
+
//.. /* 64-bit shifts */
//.. case Iop_Shl64: {
//.. /* We use the same ingenious scheme as gcc. Put the va=
lue
@@ -2180,10 +2201,10 @@
} /* if (e->tag =3D=3D Iex_Binop) */
=20
=20
-//.. /* --------- UNARY ops --------- */
-//.. if (e->tag =3D=3D Iex_Unop) {
-//.. switch (e->Iex.Unop.op) {
-//..=20
+ /* --------- UNARY ops --------- */
+ if (e->tag =3D=3D Iex_Unop) {
+ switch (e->Iex.Unop.op) {
+
//.. /* 32Sto64(e) */
//.. case Iop_32Sto64: {
//.. HReg tLo =3D newVRegI(env);
@@ -2196,19 +2217,17 @@
//.. *rLo =3D tLo;
//.. return;
//.. }
-//..=20
-//.. /* 32Uto64(e) */
-//.. case Iop_32Uto64: {
-//.. HReg tLo =3D newVRegI(env);
-//.. HReg tHi =3D newVRegI(env);
-//.. HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
-//.. addInstr(env, mk_iMOVsd_RR(src,tLo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), =
tHi));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
+
+ /* 32Uto64(e) */
+ case Iop_32Uto64: {
+ HReg tHi =3D newVRegI(env);
+ HReg tLo =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, mk_iMOVds_RRI(env, tHi, PPC32RI_Imm(0)));
+ *rHi =3D tHi;
+ *rLo =3D tLo;
+ return;
+ }
+
//.. /* 128{HI}to64 */
//.. case Iop_128HIto64:
//.. case Iop_128to64: {
@@ -2315,13 +2334,13 @@
//.. *rLo =3D tLo;
//.. return;
//.. }
-//..=20
-//.. default:=20
-//.. break;
-//.. }
-//.. } /* if (e->tag =3D=3D Iex_Unop) */
-//..=20
-//..=20
+
+ default:
+ break;
+ }
+ } /* if (e->tag =3D=3D Iex_Unop) */
+
+
//.. /* --------- CCALL --------- */
//.. if (e->tag =3D=3D Iex_CCall) {
//.. HReg tLo =3D newVRegI(env);
@@ -3192,14 +3211,15 @@
=20
/* --------- STORE --------- */
case Ist_STle: {
- PPC32AMode* am_dst;
+ PPC32AMode* am_addr;
IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.addr);
IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.data);
vassert(tya =3D=3D Ity_I32);
- am_dst =3D iselIntExpr_AMode(env, stmt->Ist.STle.addr);
+
+ am_addr =3D iselIntExpr_AMode(env, stmt->Ist.STle.addr);
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16 || tyd =3D=3D Ity_I32)=
{
HReg r_src =3D iselIntExpr_R(env, stmt->Ist.STle.data);
- addInstr(env, PPC32Instr_Store(sizeofIRType(tyd),am_dst,r_src))=
;
+ addInstr(env, PPC32Instr_Store(sizeofIRType(tyd), am_addr, r_sr=
c));
return;
}
//.. if (tyd =3D=3D Ity_F64) {
@@ -3235,8 +3255,8 @@
IRType ty =3D typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Put.data);
- PPC32AMode* am_dst =3D PPC32AMode_IR(stmt->Ist.Put.offset, Gues=
tStatePtr);
- addInstr(env, PPC32Instr_Store( sizeofIRType(ty), am_dst, r_src=
));
+ PPC32AMode* am_addr =3D PPC32AMode_IR(stmt->Ist.Put.offset, Gue=
stStatePtr);
+ addInstr(env, PPC32Instr_Store( sizeofIRType(ty), am_addr, r_sr=
c ));
return;
}
//.. if (ty =3D=3D Ity_I64) {
@@ -3339,49 +3359,59 @@
break;
}
=20
-//.. /* --------- Call to DIRTY helper --------- */
-//.. case Ist_Dirty: {
-//.. IRType retty;
-//.. IRDirty* d =3D stmt->Ist.Dirty.details;
-//.. Bool passBBP =3D False;
-//..=20
-//.. if (d->nFxState =3D=3D 0)
-//.. vassert(!d->needsBBP);
-//.. passBBP =3D d->nFxState > 0 && d->needsBBP;
-//..=20
-//.. /* Marshal args, do the call, clear stack. */
-//.. doHelperCall( env, passBBP, d->guard, d->cee, d->args );
-//..=20
-//.. /* Now figure out what to do with the returned value, if any.=
*/
-//.. if (d->tmp =3D=3D IRTemp_INVALID)
-//.. /* No return value. Nothing to do. */
-//.. return;
-//..=20
-//.. retty =3D typeOfIRTemp(env->type_env, d->tmp);
-//.. if (retty =3D=3D Ity_I64) {
-//.. HReg dstHi, dstLo;
-//.. /* The returned value is in %edx:%eax. Park it in the
-//.. register-pair associated with tmp. */
-//.. lookupIRTemp64( &dstHi, &dstLo, env, d->tmp);
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(),dstHi) );
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(),dstLo) );
-//.. return;
-//.. }
-//.. if (retty =3D=3D Ity_I32 || retty =3D=3D Ity_I16 || retty =3D=
=3D Ity_I8) {
-//.. /* The returned value is in %eax. Park it in the register
-//.. associated with tmp. */
-//.. HReg dst =3D lookupIRTemp(env, d->tmp);
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(),dst) );
-//.. return;
-//.. }
-//.. break;
-//.. }
+ /* --------- Call to DIRTY helper --------- */
+ case Ist_Dirty: {
+ IRType retty;
+ IRDirty* d =3D stmt->Ist.Dirty.details;
+ Bool passBBP =3D False;
=20
+ if (d->nFxState =3D=3D 0)
+ vassert(!d->needsBBP);
+ passBBP =3D d->nFxState > 0 && d->needsBBP;
+
+ /* Marshal args, do the call, clear stack. */
+ doHelperCall( env, passBBP, d->guard, d->cee, d->args );
+
+ /* Now figure out what to do with the returned value, if any. */
+ if (d->tmp =3D=3D IRTemp_INVALID)
+ /* No return value. Nothing to do. */
+ return;
+
+ retty =3D typeOfIRTemp(env->type_env, d->tmp);
+ if (retty =3D=3D Ity_I64) {
+ HReg r_dstHi, r_dstLo;
+ /* The returned value is in %r3:%r4. Park it in the
+ register-pair associated with tmp. */
+ lookupIRTemp64( &r_dstHi, &r_dstLo, env, d->tmp);
+ addInstr(env, mk_iMOVds_RR(r_dstHi, hregPPC32_GPR3()));
+ addInstr(env, mk_iMOVds_RR(r_dstLo, hregPPC32_GPR4()));
+ return;
+ }
+ if (retty =3D=3D Ity_I32 || retty =3D=3D Ity_I16 || retty =3D=3D I=
ty_I8) {
+ /* The returned value is in %r3. Park it in the register
+ associated with tmp. */
+ HReg r_dst =3D lookupIRTemp(env, d->tmp);
+ addInstr(env, mk_iMOVds_RR(r_dst, hregPPC32_GPR3()));
+ return;
+ }
+ break;
+ }
+
/* --------- MEM FENCE --------- */
case Ist_MFence:
addInstr(env, PPC32Instr_MFence());
return;
=20
+ /* --------- INSTR MARK --------- */
+ /* Doesn't generate any executable code ... */
+ case Ist_IMark:
+ return;
+
+ /* --------- NO-OP --------- */
+ /* Fairly self-explanatory, wouldn't you say? */
+ case Ist_NoOp:
+ return;
+
/* --------- EXIT --------- */
case Ist_Exit: {
PPC32RI* ri_dst;
@@ -3398,7 +3428,7 @@
default: break;
}
ppIRStmt(stmt);
- vpanic("iselStmt");
+ vpanic("iselStmt(ppc32)");
}
=20
=20
Modified: trunk/pub/libvex_guest_ppc32.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_guest_ppc32.h 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/pub/libvex_guest_ppc32.h 2005-06-20 12:42:04 UTC (rev 1211)
@@ -154,10 +154,11 @@
extern
void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state=
);
=20
-/* Calculate the PPC32 flag state from the saved data. */
+/* Extract from the supplied VexGuestPPC32State structure the
+ corresponding native %cr7 value. */
=20
extern
-UInt LibVEX_GuestPPC32_get_flags ( /*IN*/VexGuestPPC32State* vex_state )=
;
+UInt LibVEX_GuestPPC32_get_cr7 ( /*IN*/VexGuestPPC32State* vex_state );
=20
=20
#endif /* ndef __LIBVEX_PUB_GUEST_PPC32_H */
Modified: trunk/switchback/switchback.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/switchback/switchback.c 2005-06-20 12:15:54 UTC (rev 1210)
+++ trunk/switchback/switchback.c 2005-06-20 12:42:04 UTC (rev 1211)
@@ -302,7 +302,7 @@
}
=20
sb_helper1 =3D (HWord)&gst;
- sb_helper2 =3D LibVEX_GuestPPC32_get_flags(&gst);
+ sb_helper2 =3D LibVEX_GuestPPC32_get_cr7(&gst);
=20
/* stay sane ... */
assert(p[0] =3D=3D 24<<26); /* nop */
@@ -629,6 +629,7 @@
void log_bytes ( HChar* bytes, Int nbytes )
{
fwrite ( bytes, 1, nbytes, stdout );
+ fflush ( stdout );
}
=20
=20
|