|
From: <sv...@va...> - 2005-06-10 04:46:35
|
Author: njn
Date: 2005-06-10 05:46:19 +0100 (Fri, 10 Jun 2005)
New Revision: 3865
Log:
Put arch-specific Cachegrind code in files in the main cachegrind/
directory, instead of subdirectories. This is simpler and consistent
with how the rest of system is now structured.
Added:
trunk/cachegrind/cg-amd64.c
trunk/cachegrind/cg-arm.c
trunk/cachegrind/cg-x86.c
Removed:
trunk/cachegrind/amd64/
trunk/cachegrind/arm/
trunk/cachegrind/x86/
Modified:
trunk/cachegrind/Makefile.am
trunk/configure.in
Modified: trunk/cachegrind/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/Makefile.am 2005-06-09 23:58:36 UTC (rev 3864)
+++ trunk/cachegrind/Makefile.am 2005-06-10 04:46:19 UTC (rev 3865)
@@ -1,13 +1,5 @@
-##include $(top_srcdir)/Makefile.tool.am
-include $(top_srcdir)/Makefile.all.am
-include $(top_srcdir)/Makefile.tool-flags.am
-include $(top_srcdir)/Makefile.tool-inplace.am
+include $(top_srcdir)/Makefile.tool.am
=20
-SUBDIRS =3D $(VG_ARCH) . tests docs
-DIST_SUBDIRS =3D $(VG_ARCH_ALL) . tests docs
-
-AM_CPPFLAGS +=3D -I$(top_srcdir)/cachegrind/$(VG_ARCH)
-
bin_SCRIPTS =3D cg_annotate
=20
EXTRA_DIST =3D cg_sim.c=20
@@ -16,7 +8,8 @@
=20
val_PROGRAMS =3D vgtool_cachegrind.so
=20
-vgtool_cachegrind_so_SOURCES =3D cg_main.c
+vgtool_cachegrind_so_SOURCES =3D \
+ cg_main.c \
+ cg-@VG_ARCH@.c
vgtool_cachegrind_so_LDFLAGS =3D -shared
-vgtool_cachegrind_so_LDADD =3D ${VG_ARCH}/libcgarch.a
=20
Copied: trunk/cachegrind/cg-amd64.c (from rev 3844, trunk/cachegrind/amd6=
4/cg_arch.c)
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/amd64/cg_arch.c 2005-06-04 20:03:55 UTC (rev 3844)
+++ trunk/cachegrind/cg-amd64.c 2005-06-10 04:46:19 UTC (rev 3865)
@@ -0,0 +1,315 @@
+
+/*--------------------------------------------------------------------*/
+/*--- AMD64-specific definitions. cg-amd64.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Cachegrind, a Valgrind tool for cache
+ profiling programs.
+
+ Copyright (C) 2002-2005 Nicholas Nethercote
+ nj...@va...
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "tool.h"
+#include "cg_arch.h"
+#include "pub_tool_libcbase.h"
+#include "pub_tool_libcprint.h"
+
+// All CPUID info taken from sandpile.org/a32/cpuid.htm */
+// Probably only works for Intel and AMD chips, and probably only for so=
me of
+// them.=20
+
+static void micro_ops_warn(Int actual_size, Int used_size, Int line_size=
)
+{
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: Pentium with %d K micro-op instruction trace cache",=20
+ actual_size);
+ VG_(message)(Vg_DebugMsg,=20
+ " Simulating a %d KB cache with %d B lines",=20
+ used_size, line_size);
+}
+
+/* Intel method is truly wretched. We have to do an insane indexing int=
o an
+ * array of pre-defined configurations for various parts of the memory
+ * hierarchy.=20
+ */
+static
+Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c=
)
+{
+ UChar info[16];
+ Int i, trials;
+ Bool L2_found =3D False;
+
+ if (level < 2) {
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: CPUID level < 2 for Intel processor (%d)",=20
+ level);
+ return -1;
+ }
+
+ VG_(cpuid)(2, (Int*)&info[0], (Int*)&info[4],=20
+ (Int*)&info[8], (Int*)&info[12]);
+ trials =3D info[0] - 1; /* AL register - bits 0..7 of %eax */
+ info[0] =3D 0x0; /* reset AL */
+
+ if (0 !=3D trials) {
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: non-zero CPUID trials for Intel processor (%d)",
+ trials);
+ return -1;
+ }
+
+ for (i =3D 0; i < 16; i++) {
+
+ switch (info[i]) {
+
+ case 0x0: /* ignore zeros */
+ break;
+ =20
+ /* TLB info, ignore */
+ case 0x01: case 0x02: case 0x03: case 0x04:
+ case 0x50: case 0x51: case 0x52: case 0x5b: case 0x5c: case 0x5d:
+ case 0xb0: case 0xb3:
+ break; =20
+
+ case 0x06: *I1c =3D (cache_t) { 8, 4, 32 }; break;
+ case 0x08: *I1c =3D (cache_t) { 16, 4, 32 }; break;
+ case 0x30: *I1c =3D (cache_t) { 32, 8, 64 }; break;
+
+ case 0x0a: *D1c =3D (cache_t) { 8, 2, 32 }; break;
+ case 0x0c: *D1c =3D (cache_t) { 16, 4, 32 }; break;
+ case 0x2c: *D1c =3D (cache_t) { 32, 8, 64 }; break;
+
+ /* IA-64 info -- panic! */
+ case 0x10: case 0x15: case 0x1a:=20
+ case 0x88: case 0x89: case 0x8a: case 0x8d:
+ case 0x90: case 0x96: case 0x9b:
+ VG_(tool_panic)("IA-64 cache detected?!");
+
+ case 0x22: case 0x23: case 0x25: case 0x29:=20
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: L3 cache detected but ignored\n");
+ break;
+
+ /* These are sectored, whatever that means */
+ case 0x39: *L2c =3D (cache_t) { 128, 4, 64 }; L2_found =3D True; =
break;
+ case 0x3c: *L2c =3D (cache_t) { 256, 4, 64 }; L2_found =3D True; =
break;
+
+ /* If a P6 core, this means "no L2 cache". =20
+ If a P4 core, this means "no L3 cache".
+ We don't know what core it is, so don't issue a warning. To de=
tect
+ a missing L2 cache, we use 'L2_found'. */
+ case 0x40:
+ break;
+
+ case 0x41: *L2c =3D (cache_t) { 128, 4, 32 }; L2_found =3D True; =
break;
+ case 0x42: *L2c =3D (cache_t) { 256, 4, 32 }; L2_found =3D True; =
break;
+ case 0x43: *L2c =3D (cache_t) { 512, 4, 32 }; L2_found =3D True; =
break;
+ case 0x44: *L2c =3D (cache_t) { 1024, 4, 32 }; L2_found =3D True; =
break;
+ case 0x45: *L2c =3D (cache_t) { 2048, 4, 32 }; L2_found =3D True; =
break;
+
+ /* These are sectored, whatever that means */
+ case 0x60: *D1c =3D (cache_t) { 16, 8, 64 }; break; /* secto=
red */
+ case 0x66: *D1c =3D (cache_t) { 8, 4, 64 }; break; /* secto=
red */
+ case 0x67: *D1c =3D (cache_t) { 16, 4, 64 }; break; /* secto=
red */
+ case 0x68: *D1c =3D (cache_t) { 32, 4, 64 }; break; /* secto=
red */
+
+ /* HACK ALERT: Instruction trace cache -- capacity is micro-ops ba=
sed.
+ * conversion to byte size is a total guess; treat the 12K and 16=
K
+ * cases the same since the cache byte size must be a power of two=
for
+ * everything to work!. Also guessing 32 bytes for the line size.=
..=20
+ */
+ case 0x70: /* 12K micro-ops, 8-way */
+ *I1c =3D (cache_t) { 16, 8, 32 }; =20
+ micro_ops_warn(12, 16, 32);
+ break; =20
+ case 0x71: /* 16K micro-ops, 8-way */
+ *I1c =3D (cache_t) { 16, 8, 32 }; =20
+ micro_ops_warn(16, 16, 32);=20
+ break; =20
+ case 0x72: /* 32K micro-ops, 8-way */
+ *I1c =3D (cache_t) { 32, 8, 32 }; =20
+ micro_ops_warn(32, 32, 32);=20
+ break; =20
+
+ /* These are sectored, whatever that means */
+ case 0x79: *L2c =3D (cache_t) { 128, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7a: *L2c =3D (cache_t) { 256, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7b: *L2c =3D (cache_t) { 512, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7c: *L2c =3D (cache_t) { 1024, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7e: *L2c =3D (cache_t) { 256, 8, 128 }; L2_found =3D True;=
break;
+
+ case 0x81: *L2c =3D (cache_t) { 128, 8, 32 }; L2_found =3D True;=
break;
+ case 0x82: *L2c =3D (cache_t) { 256, 8, 32 }; L2_found =3D True;=
break;
+ case 0x83: *L2c =3D (cache_t) { 512, 8, 32 }; L2_found =3D True;=
break;
+ case 0x84: *L2c =3D (cache_t) { 1024, 8, 32 }; L2_found =3D True;=
break;
+ case 0x85: *L2c =3D (cache_t) { 2048, 8, 32 }; L2_found =3D True;=
break;
+ case 0x86: *L2c =3D (cache_t) { 512, 4, 64 }; L2_found =3D True;=
break;
+ case 0x87: *L2c =3D (cache_t) { 1024, 8, 64 }; L2_found =3D True;=
break;
+
+ default:
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: Unknown Intel cache config value "
+ "(0x%x), ignoring", info[i]);
+ break;
+ }
+ }
+
+ if (!L2_found)
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: L2 cache not installed, ignore L2 results.");
+
+ return 0;
+}
+
+/* AMD method is straightforward, just extract appropriate bits from the
+ * result registers.
+ *
+ * Bits, for D1 and I1:
+ * 31..24 data L1 cache size in KBs =20
+ * 23..16 data L1 cache associativity (FFh=3Dfull) =20
+ * 15.. 8 data L1 cache lines per tag =20
+ * 7.. 0 data L1 cache line size in bytes
+ *
+ * Bits, for L2:
+ * 31..16 unified L2 cache size in KBs
+ * 15..12 unified L2 cache associativity (0=3Doff, FFh=3Dfull)
+ * 11.. 8 unified L2 cache lines per tag =20
+ * 7.. 0 unified L2 cache line size in bytes
+ *
+ * #3 The AMD K7 processor's L2 cache must be configured prior to relyi=
ng=20
+ * upon this information. (Whatever that means -- njn)
+ *
+ * Also, according to Cyrille Chepelov, Duron stepping A0 processors (mo=
del
+ * 0x630) have a bug and misreport their L2 size as 1KB (it's really 64K=
B),
+ * so we detect that.
+ *=20
+ * Returns 0 on success, non-zero on failure.
+ */
+static
+Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
+{
+ UInt ext_level;
+ UInt dummy, model;
+ UInt I1i, D1i, L2i;
+ =20
+ VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy);
+
+ if (0 =3D=3D (ext_level & 0x80000000) || ext_level < 0x80000006) {
+ VG_(message)(Vg_UserMsg,=20
+ "warning: ext_level < 0x80000006 for AMD processor (0x%x)",=20
+ ext_level);
+ return -1;
+ }
+
+ VG_(cpuid)(0x80000005, &dummy, &dummy, &D1i, &I1i);
+ VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &dummy);
+
+ VG_(cpuid)(0x1, &model, &dummy, &dummy, &dummy);
+
+ /* Check for Duron bug */
+ if (model =3D=3D 0x630) {
+ VG_(message)(Vg_UserMsg,
+ "Buggy Duron stepping A0. Assuming L2 size=3D65536 bytes");
+ L2i =3D (64 << 16) | (L2i & 0xffff);
+ }
+
+ D1c->size =3D (D1i >> 24) & 0xff;
+ D1c->assoc =3D (D1i >> 16) & 0xff;
+ D1c->line_size =3D (D1i >> 0) & 0xff;
+
+ I1c->size =3D (I1i >> 24) & 0xff;
+ I1c->assoc =3D (I1i >> 16) & 0xff;
+ I1c->line_size =3D (I1i >> 0) & 0xff;
+
+ L2c->size =3D (L2i >> 16) & 0xffff; /* Nb: different bits used f=
or L2 */
+ L2c->assoc =3D (L2i >> 12) & 0xf;
+ L2c->line_size =3D (L2i >> 0) & 0xff;
+
+ return 0;
+}
+
+static=20
+Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
+{
+ Int level, ret;
+ Char vendor_id[13];
+
+ if (!VG_(has_cpuid)()) {
+ VG_(message)(Vg_DebugMsg, "CPUID instruction not supported");
+ return -1;
+ }
+
+ VG_(cpuid)(0, &level, (int*)&vendor_id[0],=20
+ (int*)&vendor_id[8], (int*)&vendor_id[4]); =20
+ vendor_id[12] =3D '\0';
+
+ if (0 =3D=3D level) {
+ VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n");
+ return -1;
+ }
+
+ /* Only handling Intel and AMD chips... no Cyrix, Transmeta, etc */
+ if (0 =3D=3D VG_(strcmp)(vendor_id, "GenuineIntel")) {
+ ret =3D Intel_cache_info(level, I1c, D1c, L2c);
+
+ } else if (0 =3D=3D VG_(strcmp)(vendor_id, "AuthenticAMD")) {
+ ret =3D AMD_cache_info(I1c, D1c, L2c);
+
+ } else {
+ VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)",
+ vendor_id);
+ return -1;
+ }
+
+ /* Successful! Convert sizes from KB to bytes */
+ I1c->size *=3D 1024;
+ D1c->size *=3D 1024;
+ L2c->size *=3D 1024;
+ =20
+ return ret;
+}
+
+
+void VGA_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
+ Bool all_caches_clo_defined)
+{
+ Int res;
+ =20
+ // Set caches to default.
+ *I1c =3D (cache_t) { 65536, 2, 64 };
+ *D1c =3D (cache_t) { 65536, 2, 64 };
+ *L2c =3D (cache_t) { 262144, 8, 64 };
+
+ // Then replace with any info we can get from CPUID.
+ res =3D get_caches_from_CPUID(I1c, D1c, L2c);
+
+ // Warn if CPUID failed and config not completely specified from cmd =
line.
+ if (res !=3D 0 && !all_caches_clo_defined) {
+ VG_(message)(Vg_DebugMsg,=20
+ "Warning: Couldn't auto-detect cache config, using on=
e "
+ "or more defaults ");
+ }
+}
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
Copied: trunk/cachegrind/cg-arm.c (from rev 3844, trunk/cachegrind/arm/cg=
_arch.c)
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/arm/cg_arch.c 2005-06-04 20:03:55 UTC (rev 3844)
+++ trunk/cachegrind/cg-arm.c 2005-06-10 04:46:19 UTC (rev 3865)
@@ -0,0 +1,49 @@
+
+/*--------------------------------------------------------------------*/
+/*--- ARM-specific definitions. cg-arm.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Cachegrind, a Valgrind tool for cache
+ profiling programs.
+
+ Copyright (C) 2002-2005 Nicholas Nethercote
+ nj...@va...
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "tool.h"
+#include "cg_arch.h"
+
+void VGA_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
+ Bool all_caches_clo_defined)
+{
+ // XXX: I1 and D1 are vaguely plausible, although they could really b=
e
+ // anything. However, most (all?) ARMs don't have an L2 cache. But
+ // Cachegrind assumes the presence of an L2 cache... so we just copy =
the
+ // x86 defaults. Urk.
+ *I1c =3D (cache_t) { 4096, 2, 32 };
+ *D1c =3D (cache_t) { 4096, 2, 32 };
+ *L2c =3D (cache_t) { 262144, 8, 64 };
+}
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
+
Copied: trunk/cachegrind/cg-x86.c (from rev 3844, trunk/cachegrind/x86/cg=
_arch.c)
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/x86/cg_arch.c 2005-06-04 20:03:55 UTC (rev 3844)
+++ trunk/cachegrind/cg-x86.c 2005-06-10 04:46:19 UTC (rev 3865)
@@ -0,0 +1,328 @@
+
+/*--------------------------------------------------------------------*/
+/*--- x86-specific definitions. cg-x86.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Cachegrind, a Valgrind tool for cache
+ profiling programs.
+
+ Copyright (C) 2002-2005 Nicholas Nethercote
+ nj...@va...
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "tool.h"
+#include "pub_tool_libcbase.h"
+#include "pub_tool_libcprint.h"
+#include "cg_arch.h"
+
+// All CPUID info taken from sandpile.org/a32/cpuid.htm */
+// Probably only works for Intel and AMD chips, and probably only for so=
me of
+// them.=20
+
+static void micro_ops_warn(Int actual_size, Int used_size, Int line_size=
)
+{
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: Pentium with %d K micro-op instruction trace cache",=20
+ actual_size);
+ VG_(message)(Vg_DebugMsg,=20
+ " Simulating a %d KB cache with %d B lines",=20
+ used_size, line_size);
+}
+
+/* Intel method is truly wretched. We have to do an insane indexing int=
o an
+ * array of pre-defined configurations for various parts of the memory
+ * hierarchy.=20
+ */
+static
+Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c=
)
+{
+ UChar info[16];
+ Int i, trials;
+ Bool L2_found =3D False;
+
+ if (level < 2) {
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: CPUID level < 2 for Intel processor (%d)",=20
+ level);
+ return -1;
+ }
+
+ VG_(cpuid)(2, (Int*)&info[0], (Int*)&info[4],=20
+ (Int*)&info[8], (Int*)&info[12]);
+ trials =3D info[0] - 1; /* AL register - bits 0..7 of %eax */
+ info[0] =3D 0x0; /* reset AL */
+
+ if (0 !=3D trials) {
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: non-zero CPUID trials for Intel processor (%d)",
+ trials);
+ return -1;
+ }
+
+ for (i =3D 0; i < 16; i++) {
+
+ switch (info[i]) {
+
+ case 0x0: /* ignore zeros */
+ break;
+ =20
+ /* TLB info, ignore */
+ case 0x01: case 0x02: case 0x03: case 0x04:
+ case 0x50: case 0x51: case 0x52: case 0x5b: case 0x5c: case 0x5d:
+ case 0xb0: case 0xb3:
+ break; =20
+
+ case 0x06: *I1c =3D (cache_t) { 8, 4, 32 }; break;
+ case 0x08: *I1c =3D (cache_t) { 16, 4, 32 }; break;
+ case 0x30: *I1c =3D (cache_t) { 32, 8, 64 }; break;
+
+ case 0x0a: *D1c =3D (cache_t) { 8, 2, 32 }; break;
+ case 0x0c: *D1c =3D (cache_t) { 16, 4, 32 }; break;
+ case 0x2c: *D1c =3D (cache_t) { 32, 8, 64 }; break;
+
+ /* IA-64 info -- panic! */
+ case 0x10: case 0x15: case 0x1a:=20
+ case 0x88: case 0x89: case 0x8a: case 0x8d:
+ case 0x90: case 0x96: case 0x9b:
+ VG_(tool_panic)("IA-64 cache detected?!");
+
+ case 0x22: case 0x23: case 0x25: case 0x29:=20
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: L3 cache detected but ignored\n");
+ break;
+
+ /* These are sectored, whatever that means */
+ case 0x39: *L2c =3D (cache_t) { 128, 4, 64 }; L2_found =3D True; =
break;
+ case 0x3c: *L2c =3D (cache_t) { 256, 4, 64 }; L2_found =3D True; =
break;
+
+ /* If a P6 core, this means "no L2 cache". =20
+ If a P4 core, this means "no L3 cache".
+ We don't know what core it is, so don't issue a warning. To de=
tect
+ a missing L2 cache, we use 'L2_found'. */
+ case 0x40:
+ break;
+
+ case 0x41: *L2c =3D (cache_t) { 128, 4, 32 }; L2_found =3D True; =
break;
+ case 0x42: *L2c =3D (cache_t) { 256, 4, 32 }; L2_found =3D True; =
break;
+ case 0x43: *L2c =3D (cache_t) { 512, 4, 32 }; L2_found =3D True; =
break;
+ case 0x44: *L2c =3D (cache_t) { 1024, 4, 32 }; L2_found =3D True; =
break;
+ case 0x45: *L2c =3D (cache_t) { 2048, 4, 32 }; L2_found =3D True; =
break;
+
+ /* These are sectored, whatever that means */
+ case 0x60: *D1c =3D (cache_t) { 16, 8, 64 }; break; /* secto=
red */
+ case 0x66: *D1c =3D (cache_t) { 8, 4, 64 }; break; /* secto=
red */
+ case 0x67: *D1c =3D (cache_t) { 16, 4, 64 }; break; /* secto=
red */
+ case 0x68: *D1c =3D (cache_t) { 32, 4, 64 }; break; /* secto=
red */
+
+ /* HACK ALERT: Instruction trace cache -- capacity is micro-ops ba=
sed.
+ * conversion to byte size is a total guess; treat the 12K and 16=
K
+ * cases the same since the cache byte size must be a power of two=
for
+ * everything to work!. Also guessing 32 bytes for the line size.=
..=20
+ */
+ case 0x70: /* 12K micro-ops, 8-way */
+ *I1c =3D (cache_t) { 16, 8, 32 }; =20
+ micro_ops_warn(12, 16, 32);
+ break; =20
+ case 0x71: /* 16K micro-ops, 8-way */
+ *I1c =3D (cache_t) { 16, 8, 32 }; =20
+ micro_ops_warn(16, 16, 32);=20
+ break; =20
+ case 0x72: /* 32K micro-ops, 8-way */
+ *I1c =3D (cache_t) { 32, 8, 32 }; =20
+ micro_ops_warn(32, 32, 32);=20
+ break; =20
+
+ /* These are sectored, whatever that means */
+ case 0x79: *L2c =3D (cache_t) { 128, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7a: *L2c =3D (cache_t) { 256, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7b: *L2c =3D (cache_t) { 512, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7c: *L2c =3D (cache_t) { 1024, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7e: *L2c =3D (cache_t) { 256, 8, 128 }; L2_found =3D True;=
break;
+
+ case 0x81: *L2c =3D (cache_t) { 128, 8, 32 }; L2_found =3D True;=
break;
+ case 0x82: *L2c =3D (cache_t) { 256, 8, 32 }; L2_found =3D True;=
break;
+ case 0x83: *L2c =3D (cache_t) { 512, 8, 32 }; L2_found =3D True;=
break;
+ case 0x84: *L2c =3D (cache_t) { 1024, 8, 32 }; L2_found =3D True;=
break;
+ case 0x85: *L2c =3D (cache_t) { 2048, 8, 32 }; L2_found =3D True;=
break;
+ case 0x86: *L2c =3D (cache_t) { 512, 4, 64 }; L2_found =3D True;=
break;
+ case 0x87: *L2c =3D (cache_t) { 1024, 8, 64 }; L2_found =3D True;=
break;
+
+ default:
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: Unknown Intel cache config value "
+ "(0x%x), ignoring", info[i]);
+ break;
+ }
+ }
+
+ if (!L2_found)
+ VG_(message)(Vg_DebugMsg,=20
+ "warning: L2 cache not installed, ignore L2 results.");
+
+ return 0;
+}
+
+/* AMD method is straightforward, just extract appropriate bits from the
+ * result registers.
+ *
+ * Bits, for D1 and I1:
+ * 31..24 data L1 cache size in KBs =20
+ * 23..16 data L1 cache associativity (FFh=3Dfull) =20
+ * 15.. 8 data L1 cache lines per tag =20
+ * 7.. 0 data L1 cache line size in bytes
+ *
+ * Bits, for L2:
+ * 31..16 unified L2 cache size in KBs
+ * 15..12 unified L2 cache associativity (0=3Doff, FFh=3Dfull)
+ * 11.. 8 unified L2 cache lines per tag =20
+ * 7.. 0 unified L2 cache line size in bytes
+ *
+ * #3 The AMD K7 processor's L2 cache must be configured prior to relyi=
ng=20
+ * upon this information. (Whatever that means -- njn)
+ *
+ * Also, according to Cyrille Chepelov, Duron stepping A0 processors (mo=
del
+ * 0x630) have a bug and misreport their L2 size as 1KB (it's really 64K=
B),
+ * so we detect that.
+ *=20
+ * Returns 0 on success, non-zero on failure.
+ */
+static
+Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
+{
+ UInt ext_level;
+ UInt dummy, model;
+ UInt I1i, D1i, L2i;
+ =20
+ VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy);
+
+ if (0 =3D=3D (ext_level & 0x80000000) || ext_level < 0x80000006) {
+ VG_(message)(Vg_UserMsg,=20
+ "warning: ext_level < 0x80000006 for AMD processor (0x%x)",=20
+ ext_level);
+ return -1;
+ }
+
+ VG_(cpuid)(0x80000005, &dummy, &dummy, &D1i, &I1i);
+ VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &dummy);
+
+ VG_(cpuid)(0x1, &model, &dummy, &dummy, &dummy);
+
+ /* Check for Duron bug */
+ if (model =3D=3D 0x630) {
+ VG_(message)(Vg_UserMsg,
+ "Buggy Duron stepping A0. Assuming L2 size=3D65536 bytes");
+ L2i =3D (64 << 16) | (L2i & 0xffff);
+ }
+
+ D1c->size =3D (D1i >> 24) & 0xff;
+ D1c->assoc =3D (D1i >> 16) & 0xff;
+ D1c->line_size =3D (D1i >> 0) & 0xff;
+
+ I1c->size =3D (I1i >> 24) & 0xff;
+ I1c->assoc =3D (I1i >> 16) & 0xff;
+ I1c->line_size =3D (I1i >> 0) & 0xff;
+
+ L2c->size =3D (L2i >> 16) & 0xffff; /* Nb: different bits used f=
or L2 */
+ L2c->assoc =3D (L2i >> 12) & 0xf;
+ L2c->line_size =3D (L2i >> 0) & 0xff;
+
+ return 0;
+}
+
+static=20
+Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
+{
+ Int level, ret;
+ Char vendor_id[13];
+
+ if (!VG_(has_cpuid)()) {
+ VG_(message)(Vg_DebugMsg, "CPUID instruction not supported");
+ return -1;
+ }
+
+ VG_(cpuid)(0, &level, (int*)&vendor_id[0],=20
+ (int*)&vendor_id[8], (int*)&vendor_id[4]); =20
+ vendor_id[12] =3D '\0';
+
+ if (0 =3D=3D level) {
+ VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n");
+ return -1;
+ }
+
+ /* Only handling Intel and AMD chips... no Cyrix, Transmeta, etc */
+ if (0 =3D=3D VG_(strcmp)(vendor_id, "GenuineIntel")) {
+ ret =3D Intel_cache_info(level, I1c, D1c, L2c);
+
+ } else if (0 =3D=3D VG_(strcmp)(vendor_id, "AuthenticAMD")) {
+ ret =3D AMD_cache_info(I1c, D1c, L2c);
+
+ } else if (0 =3D=3D VG_(strcmp)(vendor_id, "CentaurHauls")) {
+ /* Total kludge. Pretend to be a VIA Nehemiah. */
+ D1c->size =3D 64;
+ D1c->assoc =3D 16;
+ D1c->line_size =3D 16;
+ I1c->size =3D 64;
+ I1c->assoc =3D 4;
+ I1c->line_size =3D 16;
+ L2c->size =3D 64;
+ L2c->assoc =3D 16;
+ L2c->line_size =3D 16;
+ ret =3D 0;
+
+ } else {
+ VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)",
+ vendor_id);
+ return -1;
+ }
+
+ /* Successful! Convert sizes from KB to bytes */
+ I1c->size *=3D 1024;
+ D1c->size *=3D 1024;
+ L2c->size *=3D 1024;
+ =20
+ return ret;
+}
+
+
+void VGA_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
+ Bool all_caches_clo_defined)
+{
+ Int res;
+ =20
+ // Set caches to default.
+ *I1c =3D (cache_t) { 65536, 2, 64 };
+ *D1c =3D (cache_t) { 65536, 2, 64 };
+ *L2c =3D (cache_t) { 262144, 8, 64 };
+
+ // Then replace with any info we can get from CPUID.
+ res =3D get_caches_from_CPUID(I1c, D1c, L2c);
+
+ // Warn if CPUID failed and config not completely specified from cmd =
line.
+ if (res !=3D 0 && !all_caches_clo_defined) {
+ VG_(message)(Vg_DebugMsg,=20
+ "Warning: Couldn't auto-detect cache config, using on=
e "
+ "or more defaults ");
+ }
+}
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
Modified: trunk/configure.in
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/configure.in 2005-06-09 23:58:36 UTC (rev 3864)
+++ trunk/configure.in 2005-06-10 04:46:19 UTC (rev 3865)
@@ -444,9 +444,6 @@
memcheck/tests/x86/Makefile
memcheck/docs/Makefile
cachegrind/Makefile
- cachegrind/amd64/Makefile
- cachegrind/arm/Makefile
- cachegrind/x86/Makefile
cachegrind/tests/Makefile
cachegrind/tests/amd64/Makefile
cachegrind/tests/arm/Makefile
|