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From: John R.
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Josef Weidendorfer wrote: > the PPC ISA has no explicit call/return instructions, > so there have to be heuristics about what e.g. branch in a binary was meant > to be a call. Please give an example or two. The PowerPC does have explicit call and return instructions. Any instruction whose top 6 bits (major opcode) are 16, 18, or 19 (decimal), and whose bottom bit (the LK bit) is a 1, is a call [and/or return.] The PowerPC has conditional call and conditional return in addition to unconditional call and unconditional return. Any "computed GOTO" must use the link register (lr) or the count register (ctr) to hold the address. In particular, any return-from-subroutine [where the destination is not lexically known] is a computed GOTO which must use the count register or link register. The code for calling a shared library, generating absolute addresses from PIC code, eliminating tail recursion via branch, etc., are similarly "complex" on the PowerPC as on other architectures [such as x86.] Inlining a subroutine might be easier (because of three-address instructions and more reigsters) but is otherwise similar. The code for a C-language 'switch' is just as recognizable on PowerPC as on other architectures. The PowerPC ISA does have glaring deficiencies (cannot branch on CArry which is generated by an add or subtract [must use a compare], lacks a subtract which sets both CArry and condition codes for an unsigned operation, lacks "compare with immediate shifted by 16 bits", always sets condition codes for "and immediate", does not offer "fill low bits with ones" for "and immediate shifted", etc.) But explicit call and return are present in PowerPC ISA, and compilers use them. -- John Reiser, jreiser@BitWagon.com |