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From: Julian S. <js...@ac...> - 2007-03-12 10:57:17
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> I'm currently working on a paper, discussing valgrind from top to > bottom. What is a paper without a example, right. So I'm working a > really simple example to show the translation that valgrind performs > from x86 to IR and back again (including optimization). x86 or amd64 ? The register names you mention (rcx,rsi,rflags) are amd64 ones, not x86 ones. > PUT(%RFLAGS) = 0x8:I64 > PUT(136) = t12 > PUT(144) = t11 > PUT(%RSI) = t10 The offsets in PUT/GET are offsets into the struct VexGuestAMD64State. Have a look at the comments on its definition. There is no simulated %rflags register directly. Instead, when the flags get set, vex records the operation setting the flags (guest_CC_OP) and the operands (guest_CC_DEP1/DEP2/NDEP), so that the flags can be computed later if needed. Usually they are not needed and so this is much cheaper than computing them every time they are set. See VEX/priv/guest-amd64/gdefs.h, comment starting "%RFLAGS thunk descriptors" for more details. J |