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From: <sv...@va...> - 2005-05-12 19:22:01
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Author: sewardj
Date: 2005-05-12 20:21:55 +0100 (Thu, 12 May 2005)
New Revision: 1194
Modified:
trunk/priv/guest-amd64/toIR.c
Log:
Reinstate a bunch more x87 instructions.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-12 17:55:01 UTC (rev 1193)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-12 19:21:55 UTC (rev 1194)
@@ -4828,41 +4828,41 @@
put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL=
)));
break;
=20
-//.. case 0xE9: /* FLDL2T */
-//.. DIP("fldl2t\n");
-//.. fp_push();
-//.. /* put_ST(0, IRExpr_Const(IRConst_F64(3.321928094887=
36234781))); */
-//.. put_ST(0, IRExpr_Const(IRConst_F64i(0x400a934f0979a3=
71ULL)));
-//.. break;
-//..=20
-//.. case 0xEA: /* FLDL2E */
-//.. DIP("fldl2e\n");
-//.. fp_push();
-//.. /* put_ST(0, IRExpr_Const(IRConst_F64(1.442695040888=
96340739))); */
-//.. put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff71547652b82=
feULL)));
-//.. break;
-//..=20
-//.. case 0xEB: /* FLDPI */
-//.. DIP("fldpi\n");
-//.. fp_push();
-//.. /* put_ST(0, IRExpr_Const(IRConst_F64(3.141592653589=
79323851))); */
-//.. put_ST(0, IRExpr_Const(IRConst_F64i(0x400921fb54442d=
18ULL)));
-//.. break;
-//..=20
-//.. case 0xEC: /* FLDLG2 */
-//.. DIP("fldlg2\n");
-//.. fp_push();
-//.. /* put_ST(0, IRExpr_Const(IRConst_F64(0.301029995663=
981143))); */
-//.. put_ST(0, IRExpr_Const(IRConst_F64i(0x3fd34413509f79=
ffULL)));
-//.. break;
-//..=20
-//.. case 0xED: /* FLDLN2 */
-//.. DIP("fldln2\n");
-//.. fp_push();
-//.. /* put_ST(0, IRExpr_Const(IRConst_F64(0.693147180559=
94530942))); */
-//.. put_ST(0, IRExpr_Const(IRConst_F64i(0x3fe62e42fefa39=
efULL)));
-//.. break;
+ case 0xE9: /* FLDL2T */
+ DIP("fldl2t\n");
+ fp_push();
+ /* put_ST(0, IRExpr_Const(IRConst_F64(3.32192809488736234=
781))); */
+ put_ST(0, IRExpr_Const(IRConst_F64i(0x400a934f0979a371ULL=
)));
+ break;
=20
+ case 0xEA: /* FLDL2E */
+ DIP("fldl2e\n");
+ fp_push();
+ /* put_ST(0, IRExpr_Const(IRConst_F64(1.44269504088896340=
739))); */
+ put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff71547652b82feULL=
)));
+ break;
+
+ case 0xEB: /* FLDPI */
+ DIP("fldpi\n");
+ fp_push();
+ /* put_ST(0, IRExpr_Const(IRConst_F64(3.14159265358979323=
851))); */
+ put_ST(0, IRExpr_Const(IRConst_F64i(0x400921fb54442d18ULL=
)));
+ break;
+
+ case 0xEC: /* FLDLG2 */
+ DIP("fldlg2\n");
+ fp_push();
+ /* put_ST(0, IRExpr_Const(IRConst_F64(0.30102999566398114=
3))); */
+ put_ST(0, IRExpr_Const(IRConst_F64i(0x3fd34413509f79ffULL=
)));
+ break;
+
+ case 0xED: /* FLDLN2 */
+ DIP("fldln2\n");
+ fp_push();
+ /* put_ST(0, IRExpr_Const(IRConst_F64(0.69314718055994530=
942))); */
+ put_ST(0, IRExpr_Const(IRConst_F64i(0x3fe62e42fefa39efULL=
)));
+ break;
+
case 0xEE: /* FLDZ */
DIP("fldz\n");
fp_push();
@@ -4910,12 +4910,12 @@
//.. put_C3210( binop(Iop_PRem1C3210F64, mkexpr(a1), mkex=
pr(a2)) );
//.. break;
//.. }
-//..=20
-//.. case 0xF7: /* FINCSTP */
-//.. DIP("fprem\n");
-//.. put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) );
-//.. break;
-//..=20
+
+ case 0xF7: /* FINCSTP */
+ DIP("fincstp\n");
+ put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) );
+ break;
+
//.. case 0xF8: { /* FPREM -- not IEEE compliant */
//.. IRTemp a1 =3D newTemp(Ity_F64);
//.. IRTemp a2 =3D newTemp(Ity_F64);
@@ -4991,57 +4991,57 @@
=20
/* bits 5,4,3 are an opcode extension, and the modRM also
specifies an address. */
- //IROp fop;
- //IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ IROp fop;
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
delta +=3D len;
switch (gregLO3ofRM(modrm)) {
=20
-//.. case 0: /* FIADD m32int */ /* ST(0) +=3D m32int */
-//.. DIP("fiaddl %s\n", dis_buf);
-//.. fop =3D Iop_AddF64;
-//.. goto do_fop_m32;
-//..=20
-//.. case 1: /* FIMUL m32int */ /* ST(0) *=3D m32int */
-//.. DIP("fimull %s\n", dis_buf);
-//.. fop =3D Iop_MulF64;
-//.. goto do_fop_m32;
-//..=20
-//.. case 4: /* FISUB m32int */ /* ST(0) -=3D m32int */
-//.. DIP("fisubl %s\n", dis_buf);
-//.. fop =3D Iop_SubF64;
-//.. goto do_fop_m32;
-//..=20
-//.. case 5: /* FISUBR m32int */ /* ST(0) =3D m32int - ST(0)=
*/
-//.. DIP("fisubrl %s\n", dis_buf);
-//.. fop =3D Iop_SubF64;
-//.. goto do_foprev_m32;
-//..=20
-//.. case 6: /* FIDIV m32int */ /* ST(0) /=3D m32int */
-//.. DIP("fisubl %s\n", dis_buf);
-//.. fop =3D Iop_DivF64;
-//.. goto do_fop_m32;
-//..=20
-//.. case 7: /* FIDIVR m32int */ /* ST(0) =3D m32int / ST(0)=
*/
-//.. DIP("fidivrl %s\n", dis_buf);
-//.. fop =3D Iop_DivF64;
-//.. goto do_foprev_m32;
-//..=20
-//.. do_fop_m32:
-//.. put_ST_UNCHECKED(0,=20
-//.. binop(fop,=20
-//.. get_ST(0),
-//.. unop(Iop_I32toF64,
-//.. loadLE(Ity_I32, mkexpr(addr)))));
-//.. break;
-//..=20
-//.. do_foprev_m32:
-//.. put_ST_UNCHECKED(0,=20
-//.. binop(fop,=20
-//.. unop(Iop_I32toF64,
-//.. loadLE(Ity_I32, mkexpr(addr))),
-//.. get_ST(0)));
-//.. break;
+ case 0: /* FIADD m32int */ /* ST(0) +=3D m32int */
+ DIP("fiaddl %s\n", dis_buf);
+ fop =3D Iop_AddF64;
+ goto do_fop_m32;
=20
+ case 1: /* FIMUL m32int */ /* ST(0) *=3D m32int */
+ DIP("fimull %s\n", dis_buf);
+ fop =3D Iop_MulF64;
+ goto do_fop_m32;
+
+ case 4: /* FISUB m32int */ /* ST(0) -=3D m32int */
+ DIP("fisubl %s\n", dis_buf);
+ fop =3D Iop_SubF64;
+ goto do_fop_m32;
+
+ case 5: /* FISUBR m32int */ /* ST(0) =3D m32int - ST(0) */
+ DIP("fisubrl %s\n", dis_buf);
+ fop =3D Iop_SubF64;
+ goto do_foprev_m32;
+
+ case 6: /* FIDIV m32int */ /* ST(0) /=3D m32int */
+ DIP("fisubl %s\n", dis_buf);
+ fop =3D Iop_DivF64;
+ goto do_fop_m32;
+
+ case 7: /* FIDIVR m32int */ /* ST(0) =3D m32int / ST(0) */
+ DIP("fidivrl %s\n", dis_buf);
+ fop =3D Iop_DivF64;
+ goto do_foprev_m32;
+
+ do_fop_m32:
+ put_ST_UNCHECKED(0,=20
+ binop(fop,=20
+ get_ST(0),
+ unop(Iop_I32toF64,
+ loadLE(Ity_I32, mkexpr(addr)))));
+ break;
+
+ do_foprev_m32:
+ put_ST_UNCHECKED(0,=20
+ binop(fop,=20
+ unop(Iop_I32toF64,
+ loadLE(Ity_I32, mkexpr(addr))),
+ get_ST(0)));
+ break;
+
default:
vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
vex_printf("first_opcode =3D=3D 0xDA\n");
@@ -5133,11 +5133,11 @@
loadLE(Ity_I32, mkexpr(addr))));
break;
=20
-//.. case 2: /* FIST m32 */
-//.. DIP("fistl %s\n", dis_buf);
-//.. storeLE( mkexpr(addr),=20
-//.. binop(Iop_F64toI32, get_roundingmode(), get=
_ST(0)) );
-//.. break;
+ case 2: /* FIST m32 */
+ DIP("fistl %s\n", dis_buf);
+ storeLE( mkexpr(addr),=20
+ binop(Iop_F64toI32, get_roundingmode(), get_ST(0=
)) );
+ break;
=20
case 3: /* FISTP m32 */
DIP("fistpl %s\n", dis_buf);
@@ -5556,6 +5556,12 @@
delta++;
switch (modrm) {
=20
+ case 0xC0 ... 0xC7: /* FFREE %st(?) */
+ r_dst =3D (UInt)modrm - 0xC0;
+ DIP("ffree %%st(%u)\n", r_dst);
+ put_ST_TAG ( r_dst, mkU8(0) );
+ break;
+
//.. case 0xD0 ... 0xD7: /* FST %st(0),%st(?) */
//.. r_dst =3D (UInt)modrm - 0xD0;
//.. DIP("fst %%st(0),%%st(%d)\n", r_dst);
@@ -5614,67 +5620,68 @@
=20
if (modrm < 0xC0) {
=20
-//.. /* bits 5,4,3 are an opcode extension, and the modRM also
-//.. specifies an address. */
-//.. IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
-//.. delta +=3D len;
-//..=20
-//.. switch (gregLO3ofRM(modrm)) {
-//..=20
-//.. case 0: /* FIADD m16int */ /* ST(0) +=3D m16int */
-//.. DIP("fiaddw %s\n", dis_buf);
-//.. fop =3D Iop_AddF64;
-//.. goto do_fop_m16;
-//..=20
-//.. case 1: /* FIMUL m16int */ /* ST(0) *=3D m16int */
-//.. DIP("fimulw %s\n", dis_buf);
-//.. fop =3D Iop_MulF64;
-//.. goto do_fop_m16;
-//..=20
-//.. case 4: /* FISUB m16int */ /* ST(0) -=3D m16int */
-//.. DIP("fisubw %s\n", dis_buf);
-//.. fop =3D Iop_SubF64;
-//.. goto do_fop_m16;
-//..=20
-//.. case 5: /* FISUBR m16int */ /* ST(0) =3D m16int - ST(0)=
*/
-//.. DIP("fisubrw %s\n", dis_buf);
-//.. fop =3D Iop_SubF64;
-//.. goto do_foprev_m16;
-//..=20
-//.. case 6: /* FIDIV m16int */ /* ST(0) /=3D m16int */
-//.. DIP("fisubw %s\n", dis_buf);
-//.. fop =3D Iop_DivF64;
-//.. goto do_fop_m16;
-//..=20
-//.. case 7: /* FIDIVR m16int */ /* ST(0) =3D m16int / ST(0)=
*/
-//.. DIP("fidivrw %s\n", dis_buf);
-//.. fop =3D Iop_DivF64;
-//.. goto do_foprev_m16;
-//..=20
-//.. do_fop_m16:
-//.. put_ST_UNCHECKED(0,=20
-//.. binop(fop,=20
-//.. get_ST(0),
-//.. unop(Iop_I32toF64,
-//.. unop(Iop_16Sto32,=20
-//.. loadLE(Ity_I16, mkexpr(addr))))))=
;
-//.. break;
-//..=20
-//.. do_foprev_m16:
-//.. put_ST_UNCHECKED(0,=20
-//.. binop(fop,=20
-//.. unop(Iop_I32toF64,
-//.. unop(Iop_16Sto32,=20
-//.. loadLE(Ity_I16, mkexpr(addr)))),
-//.. get_ST(0)));
-//.. break;
-//..=20
-//.. default:
-//.. vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3o=
fRM(modrm));
-//.. vex_printf("first_opcode =3D=3D 0xDE\n");
-//.. goto decode_fail;
-//.. }
+ /* bits 5,4,3 are an opcode extension, and the modRM also
+ specifies an address. */
+ IROp fop;
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
=20
+ switch (gregLO3ofRM(modrm)) {
+
+ case 0: /* FIADD m16int */ /* ST(0) +=3D m16int */
+ DIP("fiaddw %s\n", dis_buf);
+ fop =3D Iop_AddF64;
+ goto do_fop_m16;
+
+ case 1: /* FIMUL m16int */ /* ST(0) *=3D m16int */
+ DIP("fimulw %s\n", dis_buf);
+ fop =3D Iop_MulF64;
+ goto do_fop_m16;
+
+ case 4: /* FISUB m16int */ /* ST(0) -=3D m16int */
+ DIP("fisubw %s\n", dis_buf);
+ fop =3D Iop_SubF64;
+ goto do_fop_m16;
+
+ case 5: /* FISUBR m16int */ /* ST(0) =3D m16int - ST(0) */
+ DIP("fisubrw %s\n", dis_buf);
+ fop =3D Iop_SubF64;
+ goto do_foprev_m16;
+
+ case 6: /* FIDIV m16int */ /* ST(0) /=3D m16int */
+ DIP("fisubw %s\n", dis_buf);
+ fop =3D Iop_DivF64;
+ goto do_fop_m16;
+
+ case 7: /* FIDIVR m16int */ /* ST(0) =3D m16int / ST(0) */
+ DIP("fidivrw %s\n", dis_buf);
+ fop =3D Iop_DivF64;
+ goto do_foprev_m16;
+
+ do_fop_m16:
+ put_ST_UNCHECKED(0,=20
+ binop(fop,=20
+ get_ST(0),
+ unop(Iop_I32toF64,
+ unop(Iop_16Sto32,=20
+ loadLE(Ity_I16, mkexpr(addr))))));
+ break;
+
+ do_foprev_m16:
+ put_ST_UNCHECKED(0,=20
+ binop(fop,=20
+ unop(Iop_I32toF64,
+ unop(Iop_16Sto32,=20
+ loadLE(Ity_I16, mkexpr(addr)))),
+ get_ST(0)));
+ break;
+
+ default:
+ vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
+ vex_printf("first_opcode =3D=3D 0xDE\n");
+ goto decode_fail;
+ }
+
} else {
=20
delta++;
@@ -5751,7 +5758,7 @@
//.. storeLE( mkexpr(addr),=20
//.. binop(Iop_F64toI16, get_roundingmode(), get=
_ST(0)) );
//.. break;
-//..=20
+
//.. case 3: /* FISTP m16 */
//.. DIP("fistps %s\n", dis_buf);
//.. storeLE( mkexpr(addr),=20
@@ -5767,12 +5774,12 @@
loadLE(Ity_I64, mkexpr(addr))));
break;
=20
-//.. case 7: /* FISTP m64 */
-//.. DIP("fistpll %s\n", dis_buf);
-//.. storeLE( mkexpr(addr),=20
-//.. binop(Iop_F64toI64, get_roundingmode(), get=
_ST(0)) );
-//.. fp_pop();
-//.. break;
+ case 7: /* FISTP m64 */
+ DIP("fistpll %s\n", dis_buf);
+ storeLE( mkexpr(addr),=20
+ binop(Iop_F64toI64, get_roundingmode(), get_ST(0=
)) );
+ fp_pop();
+ break;
=20
default:
vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
@@ -11666,10 +11673,10 @@
//.. //-- DIP("lahf\n");
//.. //-- break;
//.. //--=20
-//.. case 0x9B: /* FWAIT */
-//.. /* ignore? */
-//.. DIP("fwait\n");
-//.. break;
+ case 0x9B: /* FWAIT */
+ /* ignore? */
+ DIP("fwait\n");
+ break;
=20
case 0xD8:
case 0xD9:
|