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From: <sv...@va...> - 2005-04-07 02:04:05
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Author: sewardj
Date: 2005-04-07 03:03:52 +0100 (Thu, 07 Apr 2005)
New Revision: 1129
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/isel.c
Log:
Handle bsr{w,l,q} and allow bsfq.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-04-07 02:02:23 UTC (rev 1128)
+++ trunk/priv/guest-amd64/toIR.c 2005-04-07 02:03:52 UTC (rev 1129)
@@ -3330,6 +3330,7 @@
switch (sz) {
case 2: src_val &=3D 15; break;
case 4: src_val &=3D 31; break;
+ case 8: src_val &=3D 63; break;
default: *decode_OK =3D False; return delta;
}
=20
@@ -12863,9 +12864,10 @@
if (haveF2orF3(pfx)) goto decode_failure;
delta =3D dis_bs_E_G ( pfx, sz, delta, True );
break;
-//.. case 0xBD: /* BSR Gv,Ev */
-//.. delta =3D dis_bs_E_G ( sorb, sz, delta, False );
-//.. break;
+ case 0xBD: /* BSR Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta =3D dis_bs_E_G ( pfx, sz, delta, False );
+ break;
=20
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- BSWAP -=3D-=3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D */
=20
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-04-07 02:02:23 UTC (rev 1128)
+++ trunk/priv/host-amd64/isel.c 2005-04-07 02:03:52 UTC (rev 1129)
@@ -1300,21 +1300,21 @@
addInstr(env, AMD64Instr_Bsfr64(True,src,dst));
return dst;
}
-//.. case Iop_Clz32: {
-//.. /* Count leading zeroes. Do 'bsrl' to establish the in=
dex
-//.. of the highest set bit, and subtract that value from
-//.. 31. */
-//.. HReg tmp =3D newVRegI(env);
-//.. HReg dst =3D newVRegI(env);
-//.. HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
-//.. addInstr(env, X86Instr_Bsfr32(False,src,tmp));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV,=20
-//.. X86RMI_Imm(31), dst));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_SUB,
-//.. X86RMI_Reg(tmp), dst));
-//.. return dst;
-//.. }
-//..=20
+ case Iop_Clz64: {
+ /* Count leading zeroes. Do 'bsrq' to establish the index
+ of the highest set bit, and subtract that value from
+ 63. */
+ HReg tmp =3D newVRegI(env);
+ HReg dst =3D newVRegI(env);
+ HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, AMD64Instr_Bsfr64(False,src,tmp));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,=20
+ AMD64RMI_Imm(63), dst));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_SUB,
+ AMD64RMI_Reg(tmp), dst));
+ return dst;
+ }
+
//.. case Iop_128to32: {
//.. HReg dst =3D newVRegI(env);
//.. HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
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