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From: <sv...@va...> - 2005-04-07 02:01:36
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Author: sewardj
Date: 2005-04-07 03:01:23 +0100 (Thu, 07 Apr 2005)
New Revision: 1127
Modified:
trunk/priv/host-amd64/hdefs.c
Log:
Fix a nasty assembler bug, in the handling of Set64, arising from
confusion over whether we were looking at a complete integer register
number or just the lower 3 bits of it. Rename functions pertaining to
messing with integer register numbers in an attempt to stop this
happening in future.
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-04-07 01:56:21 UTC (rev 1126)
+++ trunk/priv/host-amd64/hdefs.c 2005-04-07 02:01:23 UTC (rev 1127)
@@ -1811,7 +1811,7 @@
/* --------- The amd64 assembler (bleh.) --------- */
=20
/* Produce the low three bits of an integer register number. */
-static UChar iregNo ( HReg r )
+static UChar iregBits210 ( HReg r )
{
UInt n;
vassert(hregClass(r) =3D=3D HRcInt64);
@@ -1832,7 +1832,19 @@
return toUChar((n >> 3) & 1);
}
=20
+/* Produce a complete 4-bit integer register number. */
+static UChar iregBits3210 ( HReg r )
+{
+ UInt n;
+ vassert(hregClass(r) =3D=3D HRcInt64);
+ vassert(!hregIsVirtual(r));
+ n =3D hregNumber(r);
+ vassert(n <=3D 15);
+ return toUChar(n);
+}
=20
+
+
//.. static UInt fregNo ( HReg r )
//.. {
//.. UInt n;
@@ -1936,28 +1948,31 @@
&& am->Aam.IR.reg !=3D hregAMD64_R12()=20
&& am->Aam.IR.reg !=3D hregAMD64_R13()=20
) {
- *p++ =3D mkModRegRM(0, iregNo(greg), iregNo(am->Aam.IR.reg));
+ *p++ =3D mkModRegRM(0, iregBits210(greg),=20
+ iregBits210(am->Aam.IR.reg));
return p;
}
if (fits8bits(am->Aam.IR.imm)
&& am->Aam.IR.reg !=3D hregAMD64_RSP()
&& am->Aam.IR.reg !=3D hregAMD64_R12()
) {
- *p++ =3D mkModRegRM(1, iregNo(greg), iregNo(am->Aam.IR.reg));
+ *p++ =3D mkModRegRM(1, iregBits210(greg),=20
+ iregBits210(am->Aam.IR.reg));
*p++ =3D toUChar(am->Aam.IR.imm & 0xFF);
return p;
}
if (am->Aam.IR.reg !=3D hregAMD64_RSP()
&& am->Aam.IR.reg !=3D hregAMD64_R12()
) {
- *p++ =3D mkModRegRM(2, iregNo(greg), iregNo(am->Aam.IR.reg));
+ *p++ =3D mkModRegRM(2, iregBits210(greg),=20
+ iregBits210(am->Aam.IR.reg));
p =3D emit32(p, am->Aam.IR.imm);
return p;
}
if ((am->Aam.IR.reg =3D=3D hregAMD64_RSP()
|| am->Aam.IR.reg =3D=3D hregAMD64_R12())
&& fits8bits(am->Aam.IR.imm)) {
- *p++ =3D mkModRegRM(1, iregNo(greg), 4);
+ *p++ =3D mkModRegRM(1, iregBits210(greg), 4);
*p++ =3D 0x24;
*p++ =3D toUChar(am->Aam.IR.imm & 0xFF);
return p;
@@ -1965,7 +1980,7 @@
if (/* (am->Aam.IR.reg =3D=3D hregAMD64_RSP()
|| wait for test case for RSP case */
am->Aam.IR.reg =3D=3D hregAMD64_R12()) {
- *p++ =3D mkModRegRM(2, iregNo(greg), 4);
+ *p++ =3D mkModRegRM(2, iregBits210(greg), 4);
*p++ =3D 0x24;
p =3D emit32(p, am->Aam.IR.imm);
return p;
@@ -1977,14 +1992,14 @@
if (am->tag =3D=3D Aam_IRRS) {
if (fits8bits(am->Aam.IRRS.imm)
&& am->Aam.IRRS.index !=3D hregAMD64_RSP()) {
- *p++ =3D mkModRegRM(1, iregNo(greg), 4);
+ *p++ =3D mkModRegRM(1, iregBits210(greg), 4);
*p++ =3D mkSIB(am->Aam.IRRS.shift, am->Aam.IRRS.index,=20
am->Aam.IRRS.base);
*p++ =3D toUChar(am->Aam.IRRS.imm & 0xFF);
return p;
}
if (am->Aam.IRRS.index !=3D hregAMD64_RSP()) {
- *p++ =3D mkModRegRM(2, iregNo(greg), 4);
+ *p++ =3D mkModRegRM(2, iregBits210(greg), 4);
*p++ =3D mkSIB(am->Aam.IRRS.shift, am->Aam.IRRS.index,
am->Aam.IRRS.base);
p =3D emit32(p, am->Aam.IRRS.imm);
@@ -2002,7 +2017,7 @@
/* Emit a mod-reg-rm byte when the rm bit denotes a reg. */
static UChar* doAMode_R ( UChar* p, HReg greg, HReg ereg )=20
{
- *p++ =3D mkModRegRM(3, iregNo(greg), iregNo(ereg));
+ *p++ =3D mkModRegRM(3, iregBits210(greg), iregBits210(ereg));
return p;
}
=20
@@ -2167,7 +2182,7 @@
=20
case Ain_Imm64:
*p++ =3D toUChar(0x48 + (1 & iregBit3(i->Ain.Imm64.dst)));
- *p++ =3D toUChar(0xB8 + iregNo(i->Ain.Imm64.dst));
+ *p++ =3D toUChar(0xB8 + iregBits210(i->Ain.Imm64.dst));
p =3D emit64(p, i->Ain.Imm64.imm64);
goto done;
=20
@@ -2178,7 +2193,7 @@
case Armi_Imm:
*p++ =3D toUChar(0x48 + (1 & iregBit3(i->Ain.Alu64R.dst))=
);
*p++ =3D 0xC7;
- *p++ =3D toUChar(0xC0 + iregNo(i->Ain.Alu64R.dst));
+ *p++ =3D toUChar(0xC0 + iregBits210(i->Ain.Alu64R.dst));
p =3D emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
goto done;
case Armi_Reg:
@@ -2513,7 +2528,7 @@
goto done;
case Armi_Reg:
*p++ =3D toUChar(0x40 + (1 & iregBit3(i->Ain.Push.src->Armi.=
Reg.reg)));
- *p++ =3D toUChar(0x50 + iregNo(i->Ain.Push.src->Armi.Reg.reg=
));
+ *p++ =3D toUChar(0x50 + iregBits210(i->Ain.Push.src->Armi.Re=
g.reg));
goto done;
default:=20
goto bad;
@@ -2677,8 +2692,7 @@
of the destination should be forced to zero, but doing 'xorq
%r,%r' kills the flag(s) we are about to read. Sigh. So
start off my moving $0 into the dest. */
-
- reg =3D iregNo(i->Ain.Set64.dst);
+ reg =3D iregBits3210(i->Ain.Set64.dst);
vassert(reg < 16);
=20
/* movq $0, %dst */
@@ -2932,7 +2946,7 @@
*p++ =3D 0x9C;
/* popq %dst */
*p++ =3D toUChar(0x40 + (1 & iregBit3(i->Ain.SseUComIS.dst)));
- *p++ =3D toUChar(0x58 + iregNo(i->Ain.SseUComIS.dst));
+ *p++ =3D toUChar(0x58 + iregBits210(i->Ain.SseUComIS.dst));
goto done;
=20
case Ain_SseSI2SF:
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