Re: [Valgrind-users] Core2 support in cachegrind

[Nicholas N. <nj...@cs...>]

On Wed, 22 Nov 2006, Josef Weidendorfer wrote:

> Intel seems to be reusing numbers if the cache parameters match exactly.
> Here, the reuse is for (4MB, 16-way associative, 64 byte line size) either
> for the 2nd or 3rd level (Xeon MP, Family F, Model 6).
>
> I think we should use your version.
> Nick?

You know better than I do :)  Sounds good, Josef, would you mind committing 
the improvement to both Cachegrind and Callgrind?  Thanks.

Nick