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From: <sv...@va...> - 2005-04-02 17:26:11
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Author: tom
Date: 2005-04-02 18:26:07 +0100 (Sat, 02 Apr 2005)
New Revision: 3508
Modified:
trunk/cachegrind/amd64/cg_arch.c
Log:
Make cache detection work on amd64.
Modified: trunk/cachegrind/amd64/cg_arch.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/amd64/cg_arch.c 2005-04-02 17:25:34 UTC (rev 3507)
+++ trunk/cachegrind/amd64/cg_arch.c 2005-04-02 17:26:07 UTC (rev 3508)
@@ -35,7 +35,6 @@
// Probably only works for Intel and AMD chips, and probably only for so=
me of
// them.=20
=20
-#if 0
static void micro_ops_warn(Int actual_size, Int used_size, Int line_size=
)
{
VG_(message)(Vg_DebugMsg,=20
@@ -246,48 +245,19 @@
return 0;
}
=20
-static jmp_buf cpuid_jmpbuf;
-
-static
-void cpuid_SIGILL_handler(int signum)
-{
- __builtin_longjmp(cpuid_jmpbuf, 1);
-}
-
static=20
Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
{
- Int level, res, ret;
+ Int level, ret;
Char vendor_id[13];
- struct vki_sigaction sigill_new, sigill_saved;
-
- /* Install own SIGILL handler */
- sigill_new.ksa_handler =3D cpuid_SIGILL_handler;
- sigill_new.sa_flags =3D 0;
- sigill_new.sa_restorer =3D NULL;
- res =3D VG_(sigemptyset)( &sigill_new.sa_mask );
- tl_assert(res =3D=3D 0);
-
- res =3D VG_(sigaction)( VKI_SIGILL, &sigill_new, &sigill_saved );
- tl_assert(res =3D=3D 0);
-
/* Trap for illegal instruction, in case it's a really old processor =
that
* doesn't support CPUID. */
- if (__builtin_setjmp(cpuid_jmpbuf) =3D=3D 0) {
+ if (VG_(has_cpuid)()) {
VG_(cpuid)(0, &level, (int*)&vendor_id[0],=20
(int*)&vendor_id[8], (int*)&vendor_id[4]); =
=20
vendor_id[12] =3D '\0';
-
- /* Restore old SIGILL handler */
- res =3D VG_(sigaction)( VKI_SIGILL, &sigill_saved, NULL );
- tl_assert(res =3D=3D 0);
-
} else {
VG_(message)(Vg_DebugMsg, "CPUID instruction not supported");
-
- /* Restore old SIGILL handler */
- res =3D VG_(sigaction)( VKI_SIGILL, &sigill_saved, NULL );
- tl_assert(res =3D=3D 0);
return -1;
}
=20
@@ -303,19 +273,6 @@
} else if (0 =3D=3D VG_(strcmp)(vendor_id, "AuthenticAMD")) {
ret =3D AMD_cache_info(I1c, D1c, L2c);
=20
- } else if (0 =3D=3D VG_(strcmp)(vendor_id, "CentaurHauls")) {
- /* Total kludge. Pretend to be a VIA Nehemiah. */
- D1c->size =3D 64;
- D1c->assoc =3D 16;
- D1c->line_size =3D 16;
- I1c->size =3D 64;
- I1c->assoc =3D 4;
- I1c->line_size =3D 16;
- L2c->size =3D 64;
- L2c->assoc =3D 16;
- L2c->line_size =3D 16;
- ret =3D 0;
-
} else {
VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)",
vendor_id);
@@ -329,24 +286,11 @@
=20
return ret;
}
-#endif
=20
=20
void VGA_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
Bool all_caches_clo_defined)
{
- // Set caches to default.
- *I1c =3D (cache_t) { 65536, 2, 64 };
- *D1c =3D (cache_t) { 65536, 2, 64 };
- *L2c =3D (cache_t) { 524288, 8, 64 };
-
- if (1) {
- VG_(message)(Vg_DebugMsg,=20
- "Warning: Couldn't auto-detect cache config, using on=
e "
- "or more defaults ");
- }
-
-#if 0
Int res;
=20
// Set caches to default.
@@ -363,7 +307,6 @@
"Warning: Couldn't auto-detect cache config, using on=
e "
"or more defaults ");
}
-#endif
}
=20
/*--------------------------------------------------------------------*/
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