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From: Jeremy F. <je...@go...> - 2004-12-16 23:03:25
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On Wed, 2004-12-15 at 18:31 +0000, Julian Seward wrote: > What one might interpret it to mean is that this is a microarchitectural > hack from Intel. The different variants of each instruction effectively > give a hint about which forwarding path the instruction's results > should be sent along. If you keep the types consistent, data might get > to the next functional unit (or whatever) sooner; if you mix up types, > the results are still the same, but results have to be shunted along > longer, slower forwarding paths. > > Any microarchitects out there have a clue about this? Further confirmation: the Athlon64 performance counter documentation lists events for "SSE reclass microfaults" and "SSE retype microfaults". J |