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From: Jeremy F. <je...@go...> - 2004-12-07 17:18:45
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On Fri, 2004-12-03 at 18:31 -0800, Roland McGrath wrote: > That > is, when you hit a segment register load instruction or an intersegment > jump/call instruction, stop the world, possibly throw away all your cached > translations, and switch to the slower plan where the translated code does > the segmented->linear translation work. Yep. > You just want the translation cache to remain in terms of linear eip Yep. > This is another thing that is straightforward and that in practice probably > noone will ever ask us to do. That is, 16-bit mode. If we have a > pure-virtual valgrind for xen/x86-64, it should support going into 32-bit > user mode. Keeping the translations straight is simple; you just need to > include some mode bits from the segmentation universe along with the linear > address in what constitutes the lhs of the translation cache. More of the > work is making the translator understand the 64-bit (16-bit) instruction > set you get in 64-bit mode. With x86-64, you could use some of the address bits to tag the code type (either by assuming that we're only using 48 address bits, or by using a >64bit cache tag). J |