Index: memcheck/mc_main.c =================================================================== --- memcheck/mc_main.c (revision 5426) +++ memcheck/mc_main.c (working copy) @@ -748,6 +748,11 @@ /* --------------- Load/store slow cases. --------------- */ +static void oink ( HWord sz) +{ + MC_(helperc_complain_undef) ( sz ); +} + // Forward declarations static void mc_record_address_error ( ThreadId tid, Addr a, Int size, Bool isWrite ); @@ -763,6 +768,7 @@ valid addresses and Defined for invalid addresses. Iterate over the bytes in the word, from the most significant down to the least. */ + Bool foo = False; ULong vbits64 = V_BITS64_INVALID; SSizeT i = szB-1; // Must be signed SizeT n_addrs_bad = 0; @@ -779,13 +785,14 @@ vabits8 = get_vabits8(ai); // Convert the in-memory format to in-register format. if ( VA_BITS8_READABLE == vabits8 ) { vbits8 = V_BITS8_VALID; } - else if ( VA_BITS8_WRITABLE == vabits8 ) { vbits8 = V_BITS8_INVALID; } + else if ( VA_BITS8_WRITABLE == vabits8 ) { foo=True;vbits8 = V_BITS8_VALID; } else if ( VA_BITS8_NOACCESS == vabits8 ) { vbits8 = V_BITS8_VALID; // Make V bits defined! n_addrs_bad++; } else { tl_assert( VA_BITS8_OTHER == vabits8 ); vbits8 = get_sec_vbits8(ai); + foo=True; } vbits64 <<= 8; vbits64 |= vbits8; @@ -812,6 +819,8 @@ if (n_addrs_bad > 0 && !partial_load_exemption_applies) mc_record_address_error( VG_(get_running_tid)(), a, szB, False ); + if (foo) oink(szB); + return vbits64; } @@ -2744,7 +2753,7 @@ if (EXPECTED_TAKEN(vabits64 == VA_BITS64_READABLE)) { return V_BITS64_VALID; } else if (EXPECTED_TAKEN(vabits64 == VA_BITS64_WRITABLE)) { - return V_BITS64_INVALID; + oink(8); return V_BITS64_VALID; } else { /* Slow case: the 8 bytes are not all-readable or all-writable. */ PROF_EVENT(202, "mc_LOADV8-slow2"); @@ -2854,7 +2863,8 @@ if (EXPECTED_TAKEN(vabits32 == VA_BITS32_READABLE)) { return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_VALID); } else if (EXPECTED_TAKEN(vabits32 == VA_BITS32_WRITABLE)) { - return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_INVALID); + oink(4); + return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_VALID); } else { /* Slow case: the 4 bytes are not all-readable or all-writable. */ PROF_EVENT(222, "mc_LOADV4-slow2"); @@ -2992,13 +3002,13 @@ // Convert V bits from compact memory form to expanded register form // XXX: set the high 16/48 bits of retval to 1 for 64-bit paranoia? if (vabits32 == VA_BITS32_READABLE) { return V_BITS16_VALID; } - else if (vabits32 == VA_BITS32_WRITABLE) { return V_BITS16_INVALID; } + else if (vabits32 == VA_BITS32_WRITABLE) { oink(2);return V_BITS16_VALID; } else { // The 4 (yes, 4) bytes are not all-readable or all-writable, check // the two sub-bytes. UChar vabits16 = extract_vabits16_from_vabits32(a, vabits32); if (vabits16 == VA_BITS16_READABLE) { return V_BITS16_VALID; } - else if (vabits16 == VA_BITS16_WRITABLE) { return V_BITS16_INVALID; } + else if (vabits16 == VA_BITS16_WRITABLE) { oink(2);return V_BITS16_VALID; } else { /* Slow case: the two bytes are not all-readable or all-writable. */ PROF_EVENT(242, "mc_LOADV2-slow2"); @@ -3106,13 +3116,13 @@ // word32 it lives in is addressible. // XXX: set the high 24/56 bits of retval to 1 for 64-bit paranoia? if (vabits32 == VA_BITS32_READABLE) { return V_BITS8_VALID; } - else if (vabits32 == VA_BITS32_WRITABLE) { return V_BITS8_INVALID; } + else if (vabits32 == VA_BITS32_WRITABLE) { oink(1);return V_BITS8_VALID; } else { // The 4 (yes, 4) bytes are not all-readable or all-writable, check // the single byte. UChar vabits8 = extract_vabits8_from_vabits32(a, vabits32); if (vabits8 == VA_BITS8_READABLE) { return V_BITS8_VALID; } - else if (vabits8 == VA_BITS8_WRITABLE) { return V_BITS8_INVALID; } + else if (vabits8 == VA_BITS8_WRITABLE) { oink(1);return V_BITS8_VALID; } else { /* Slow case: the byte is not all-readable or all-writable. */ PROF_EVENT(262, "mc_LOADV1-slow2"); @@ -4198,3 +4208,4 @@ /*--------------------------------------------------------------------*/ /*--- end ---*/ /*--------------------------------------------------------------------*/ +