================================================= ./valgrind-new/cachegrind/tests/chdir.stderr.diff ================================================= --- chdir.stderr.exp 2009-10-28 03:23:19.000000000 +0000 +++ chdir.stderr.out 2009-10-28 03:28:58.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-new/cachegrind/tests/clreq.stderr.diff ================================================= --- clreq.stderr.exp 2009-10-28 03:23:19.000000000 +0000 +++ clreq.stderr.out 2009-10-28 03:28:58.000000000 +0000 @@ -0,0 +1,8 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. ================================================= ./valgrind-new/cachegrind/tests/dlclose.stderr.diff ================================================= --- dlclose.stderr.exp 2009-10-28 03:23:19.000000000 +0000 +++ dlclose.stderr.out 2009-10-28 03:28:59.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-new/cachegrind/tests/notpower2.stderr.diff ================================================= --- notpower2.stderr.exp 2009-10-28 03:23:19.000000000 +0000 +++ notpower2.stderr.out 2009-10-28 03:28:59.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-new/cachegrind/tests/wrap5.stderr.diff ================================================= --- wrap5.stderr.exp 2009-10-28 03:23:19.000000000 +0000 +++ wrap5.stderr.out 2009-10-28 03:28:59.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-new/cachegrind/tests/x86/fpu-28-108.stderr.diff ================================================= --- fpu-28-108.stderr.exp 2009-10-28 03:23:19.000000000 +0000 +++ fpu-28-108.stderr.out 2009-10-28 03:29:00.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-new/callgrind/tests/notpower2-hwpref.stderr.diff ================================================= --- notpower2-hwpref.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ notpower2-hwpref.stderr.out 2009-10-28 03:29:00.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Collected : ================================================= ./valgrind-new/callgrind/tests/notpower2-use.stderr.diff ================================================= --- notpower2-use.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ notpower2-use.stderr.out 2009-10-28 03:29:00.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 Collected : ================================================= ./valgrind-new/callgrind/tests/notpower2-wb.stderr.diff ================================================= --- notpower2-wb.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ notpower2-wb.stderr.out 2009-10-28 03:29:00.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw Collected : ================================================= ./valgrind-new/callgrind/tests/notpower2.stderr.diff ================================================= --- notpower2.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ notpower2.stderr.out 2009-10-28 03:29:01.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Collected : ================================================= ./valgrind-new/callgrind/tests/simwork1.stderr.diff ================================================= --- simwork1.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ simwork1.stderr.out 2009-10-28 03:29:01.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Collected : ================================================= ./valgrind-new/callgrind/tests/simwork2.stderr.diff ================================================= --- simwork2.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ simwork2.stderr.out 2009-10-28 03:29:02.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw Collected : ================================================= ./valgrind-new/callgrind/tests/simwork3.stderr.diff ================================================= --- simwork3.stderr.exp 2009-10-28 03:23:13.000000000 +0000 +++ simwork3.stderr.out 2009-10-28 03:29:03.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 Collected : ================================================= ./valgrind-new/helgrind/tests/tc06_two_races_xml.stderr.diff ================================================= --- tc06_two_races_xml.stderr.exp 2009-10-28 03:23:12.000000000 +0000 +++ tc06_two_races_xml.stderr.out 2009-10-28 03:31:21.000000000 +0000 @@ -29,12 +29,12 @@ - 1 + 1 - 2 + 2 0x........ @@ -44,12 +44,10 @@ 0x........ ... - do_clone - - - 0x........ - ... pthread_create@@GLIBC_2.2.5 + ... + createthread.c + ... 0x........ @@ -121,6 +119,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -175,6 +176,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -229,6 +233,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -283,6 +290,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -294,6 +304,7 @@ declared at tc06_two_races.c:9 tc06_two_races.c ... + FINISHED ================================================= ./valgrind-new/memcheck/tests/linux/sigqueue.stderr.diff ================================================= --- sigqueue.stderr.exp 2009-10-28 03:23:15.000000000 +0000 +++ sigqueue.stderr.out 2009-10-28 03:27:31.000000000 +0000 @@ -1,6 +1,12 @@ sizeof(*si) = 128 0 4 8 16 +Syscall param rt_sigqueueinfo(uinfo) points to unaddressable byte(s) + ... + Address 0x........ is 0 bytes after a block of size 128 alloc'd + at 0x........: calloc (vg_replace_malloc.c:...) + by 0x........: main (sigqueue.c:21) + Done. HEAP SUMMARY: ================================================= ./valgrind-old/cachegrind/tests/chdir.stderr.diff ================================================= --- chdir.stderr.exp 2009-10-28 03:10:13.000000000 +0000 +++ chdir.stderr.out 2009-10-28 03:16:07.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-old/cachegrind/tests/clreq.stderr.diff ================================================= --- clreq.stderr.exp 2009-10-28 03:10:13.000000000 +0000 +++ clreq.stderr.out 2009-10-28 03:16:07.000000000 +0000 @@ -0,0 +1,8 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. ================================================= ./valgrind-old/cachegrind/tests/dlclose.stderr.diff ================================================= --- dlclose.stderr.exp 2009-10-28 03:10:13.000000000 +0000 +++ dlclose.stderr.out 2009-10-28 03:16:07.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-old/cachegrind/tests/notpower2.stderr.diff ================================================= --- notpower2.stderr.exp 2009-10-28 03:10:13.000000000 +0000 +++ notpower2.stderr.out 2009-10-28 03:16:08.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-old/cachegrind/tests/wrap5.stderr.diff ================================================= --- wrap5.stderr.exp 2009-10-28 03:10:13.000000000 +0000 +++ wrap5.stderr.out 2009-10-28 03:16:08.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-old/cachegrind/tests/x86/fpu-28-108.stderr.diff ================================================= --- fpu-28-108.stderr.exp 2009-10-28 03:10:12.000000000 +0000 +++ fpu-28-108.stderr.out 2009-10-28 03:16:08.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. I refs: I1 misses: ================================================= ./valgrind-old/callgrind/tests/notpower2-hwpref.stderr.diff ================================================= --- notpower2-hwpref.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ notpower2-hwpref.stderr.out 2009-10-28 03:16:09.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Collected : ================================================= ./valgrind-old/callgrind/tests/notpower2-use.stderr.diff ================================================= --- notpower2-use.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ notpower2-use.stderr.out 2009-10-28 03:16:09.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 Collected : ================================================= ./valgrind-old/callgrind/tests/notpower2-wb.stderr.diff ================================================= --- notpower2-wb.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ notpower2-wb.stderr.out 2009-10-28 03:16:09.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw Collected : ================================================= ./valgrind-old/callgrind/tests/notpower2.stderr.diff ================================================= --- notpower2.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ notpower2.stderr.out 2009-10-28 03:16:09.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Collected : ================================================= ./valgrind-old/callgrind/tests/simwork1.stderr.diff ================================================= --- simwork1.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ simwork1.stderr.out 2009-10-28 03:16:10.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Collected : ================================================= ./valgrind-old/callgrind/tests/simwork2.stderr.diff ================================================= --- simwork2.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ simwork2.stderr.out 2009-10-28 03:16:11.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw Collected : ================================================= ./valgrind-old/callgrind/tests/simwork3.stderr.diff ================================================= --- simwork3.stderr.exp 2009-10-28 03:10:10.000000000 +0000 +++ simwork3.stderr.out 2009-10-28 03:16:12.000000000 +0000 @@ -1,4 +1,12 @@ +warning: Unknown Intel cache config value (0x5a), ignoring +warning: Unknown Intel cache config value (0x55), ignoring +warning: Unknown Intel cache config value (0xe4), ignoring +warning: Unknown Intel cache config value (0xb2), ignoring +warning: Unknown Intel cache config value (0x21), ignoring +warning: Unknown Intel cache config value (0xca), ignoring +warning: Unknown Intel cache config value (0x9), ignoring +warning: L2 cache not installed, ignore L2 results. Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 Collected : ================================================= ./valgrind-old/helgrind/tests/tc06_two_races_xml.stderr.diff ================================================= --- tc06_two_races_xml.stderr.exp 2009-10-28 03:10:09.000000000 +0000 +++ tc06_two_races_xml.stderr.out 2009-10-28 03:18:30.000000000 +0000 @@ -29,12 +29,12 @@ - 1 + 1 - 2 + 2 0x........ @@ -44,12 +44,10 @@ 0x........ ... - do_clone - - - 0x........ - ... pthread_create@@GLIBC_2.2.5 + ... + createthread.c + ... 0x........ @@ -121,6 +119,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -175,6 +176,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -229,6 +233,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -283,6 +290,9 @@ 0x........ ... start_thread + ... + pthread_create.c + ... 0x........ @@ -294,6 +304,7 @@ declared at tc06_two_races.c:9 tc06_two_races.c ... + FINISHED