Index: none/tests/arm64/memory.c
===================================================================
--- none/tests/arm64/memory.c	(revision 16098)
+++ none/tests/arm64/memory.c	(working copy)
@@ -155,6 +155,13 @@
 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
 
+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+
 ////////////////////////////////////////////////////////////////
 // This is a bit tricky.  We load the value from just before and
 // just after the actual instruction.  So we place a couple of
Index: none/tests/arm64/memory.stdout.exp
===================================================================
--- none/tests/arm64/memory.stdout.exp	(revision 16098)
+++ none/tests/arm64/memory.stdout.exp	(working copy)
@@ -20,6 +20,12 @@
 ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
 ldp w21, w28, [x22, #-40] ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000     
 ldp w21, w28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd ffffffffebe9e7e4 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
 LDR (literal, int reg)
 nop; nop; nop; xyzzy00: ldr  x21, xyzzy00 - 8; nop; nop; nop :: rd d503201fd503201f rn (hidden), cin 0, nzcv 00000000     
 nop; nop; nop; xyzzy01: ldr  x21, xyzzy01 + 0; nop; nop; nop :: rd d503201f58000015 rn (hidden), cin 0, nzcv 00000000     
@@ -26356,3 +26362,94 @@
                  0  x5       (sub, base reg)
                  0  x6       (sub, index reg)
 
+LDPSW
+ldpsw x13, x23, [x5], #-24  with  x5 = middle_of_block+0,  x6=0
+  [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 32]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 48]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 64]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 80]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 96]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [112]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [128]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [144]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [160]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [176]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [192]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [208]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [224]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [240]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  30be48517f1c1aa9  x13      (xor, xfer intreg #1)
+  0aaacd7a281aa7c7  x23      (xor, xfer intreg #2)
+  0000000000000000  v17.d[0] (xor, xfer vecreg #1)
+  0000000000000000  v17.d[1] (xor, xfer vecreg #1)
+  0000000000000000  v18.d[0] (xor, xfer vecreg #2)
+  0000000000000000  v18.d[1] (xor, xfer vecreg #2)
+  0000000000000000  v19.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v19.d[1] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[1] (xor, xfer vecreg #3)
+               -24  x5       (sub, base reg)
+                 0  x6       (sub, index reg)
+
+ldpsw x13, x23, [x5, #-40]!  with  x5 = middle_of_block+0,  x6=0
+  [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 32]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 48]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 64]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 80]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 96]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [112]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [128]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [144]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [160]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [176]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [192]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [208]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [224]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [240]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  253ca656b2adb962  x13      (xor, xfer intreg #1)
+  e8672de280f284ed  x23      (xor, xfer intreg #2)
+  0000000000000000  v17.d[0] (xor, xfer vecreg #1)
+  0000000000000000  v17.d[1] (xor, xfer vecreg #1)
+  0000000000000000  v18.d[0] (xor, xfer vecreg #2)
+  0000000000000000  v18.d[1] (xor, xfer vecreg #2)
+  0000000000000000  v19.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v19.d[1] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[1] (xor, xfer vecreg #3)
+               -40  x5       (sub, base reg)
+                 0  x6       (sub, index reg)
+
+ldpsw x13, x23, [x5, #-40]  with  x5 = middle_of_block+0,  x6=0
+  [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 32]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 48]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 64]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 80]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 96]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [112]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [128]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [144]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [160]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [176]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [192]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [208]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [224]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [240]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  c23358ad272cc2dc  x13      (xor, xfer intreg #1)
+  ebff55f813a3da06  x23      (xor, xfer intreg #2)
+  0000000000000000  v17.d[0] (xor, xfer vecreg #1)
+  0000000000000000  v17.d[1] (xor, xfer vecreg #1)
+  0000000000000000  v18.d[0] (xor, xfer vecreg #2)
+  0000000000000000  v18.d[1] (xor, xfer vecreg #2)
+  0000000000000000  v19.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v19.d[1] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[1] (xor, xfer vecreg #3)
+                 0  x5       (sub, base reg)
+                 0  x6       (sub, index reg)
+
