For anyone wondering what's happening with this project, here's an update:
Development got stalled due to day jobs, but I did spend a lot of time working on the SystemVerilog standard. I realized that there wasn't much future in SystemVerilog as an ESL language because no programmers will use it. Likewise SystemC is a severely deficient approach to using a programming language for hardware design.
I decided that the obvious ESL solution was to extend C++ with useful HDL features i.e. direct lightweight multithreading support.
In the same time frame CPU manufacturers have moved to multicore, so I'm working making it handle parallel processing issues too.
The code for the extended C++ parser is in the repository, get in touch with me if you are interested in working on it. The next goal of the project will probably be to translate Verilog into the new C++ dialect to provide real simulation.
Kev.