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Unified Verification Environment (UVE)

The aim of the UVE project is to create software that automatically generates
a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology.

UVE makes the rapid development of a verification environment a simple process.
The generated TB is directly able to perform random actions on the DUV (design
under verification). For this UVE provides a graphical user interface, a code
generator, compilation scripts and a library of verification IPs (VIP). One of
the main innovations of UVE is a list of TODOs in the TB code which help in
finalizing the TB. This is especially useful for developers not familiar with
SV and/or UVE, but also experienced developers profit from that easy to use
task list.

Moreover, the graphical interface lets the user observe the structure of the
generated testbench. Files can be accessed easily by double clicking on the
graphical view. Simulation can be launched directly from the tool.

For more information visit our homepage: www.systemverilog.ch

Project Members:

• guo (admin)