Using URJTAG to communicate with BSCAN_SPARTAN3?

hjf
2014-02-18
2014-02-18
  • hjf

    hjf - 2014-02-18

    I would like to use URJTAG and my BusBlaster interface to access a the BSCAN_SPARTAN3 interface.

    I found some example implementation on the web:

    process(DRCK1,UPDATE,SEL1)
    begin

        if SEL1='1' then
    
            if UPDATE='1' then
                led <= shiftreg;
    
            elsif CAPTURE='1' then
                shiftreg <= switches;
    
            elsif rising_edge(DRCK1) then
                shiftreg <= TDI & shiftreg(7 downto 1);
    
            end if;
    
        end if;
    end process;
    

    Now, to access via URJTAG I do this:

    jtag> register UR 8
    Data register 'UR' already defined
    jtag> instruction USER1 000010 UR
    Instruction 'USER1' already defined
    jtag> part 0
    jtag> INSTRUCTION BYPASS
    jtag> part 1
    jtag> instruction USER1
    jtag> shift ir
    jtag> shift dr
    jtag> dr
    10101010
    jtag> shift dr
    jtag> dr
    00000000

    As you can see, the first time, it answers. But then it returns all zeros. It's as if CAPTURE is never toggled so the contents of "switches" is never loaded.

    If i define USER2 instruction, shift it, then shift USER1 instruction again, it works (only once, of course).

    Maybe I'm using urjtag wrong?

     
    • Arnim Läuger

      Arnim Läuger - 2014-02-18

      I would like to use URJTAG and my BusBlaster interface to access a the
      BSCAN_SPARTAN3 interface.

      I found some example implementation on the web:

      process(DRCK1,UPDATE,SEL1)
      begin

      if SEL1='1' then
      
          if UPDATE='1' then
              led <= shiftreg;
      
          elsif CAPTURE='1' then
              shiftreg <= switches;
      
          elsif rising_edge(DRCK1) then
              shiftreg <= TDI & shiftreg(7 downto 1);
      
          end if;
      
      end if;
      

      end process;

      I'd propose to separate the shift/capture part from the update part in
      the two processes. Mainly because you look at different clocks here.
      DRCK1 is the clock for shift/capture:

      process (DRCK1)
      begin
      -- reset flip-flops if required
      if rising_edge(DRCK1) then
      if SEL1 = '1' then
      if SHIFT = '1' then
      shiftreg <= TDI & shiftreg(7 downto 1);
      else
      shiftreg <= switches;
      end if;
      end if;
      end if;
      end process;

      While UPDATE is the other clock:
      process (UPDATE)
      begin
      -- reset flip-flops if required
      if rising_edge(UPDATE) then
      if SEL1 = '1' then
      led <= shiftreg;
      end if;
      end if;
      end process;

      Now, to access via URJTAG I do this:

      jtag> register UR 8
      Data register 'UR' already defined
      jtag> instruction USER1 000010 UR
      Instruction 'USER1' already defined
      jtag> part 0
      jtag> INSTRUCTION BYPASS
      jtag> part 1
      jtag> instruction USER1
      jtag> shift ir
      jtag> shift dr
      jtag> dr
      10101010
      jtag> shift dr
      jtag> dr
      00000000

      As you can see, the first time, it answers. But then it returns all
      zeros. It's as if CAPTURE is never toggled so the contents of "switches"
      is never loaded.

      Your proposed VHDL process has severe challenges for implementation
      since you mix latch style (enable by CAPTURE) with flip-flop style
      (clock by DRCK1) for shiftreg. I could imagine that this results in a
      somewhat messy timing situation on gate level while it might work in
      simulation.

      Examples for using BSCAN_SPARTAN3 with the fjmem bus driver can be found
      in the extra section:
      http://sourceforge.net/p/urjtag/svn/HEAD/tree/trunk/urjtag/extra/fjmem/

      Maybe I'm using urjtag wrong?

      Seems ok so far. However, your log shows that UR and USER1 are already
      defined. Did you specify these commands already before or are they
      loaded from some definition file?

      Best regards,
      Arnim

       

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