I'm having some trouble programming an Altera EPM7064SLC44-10 CPLD.
I converted Alteras BSDL file with bsdl2jtag, and I'm using a Xilinx DLC5 and UrJTAG 0.10 #2017 on Fedora 19.
I can detect the part just fine (after some fiddling - I think Alteras datasheets have the incorrect IDCODE for the EPM3064 parts, but that's another problem entirely):
jtag> cable DLC5 ppdev /dev/parport0
Initializing ppdev port /dev/parport0
IR length: 10
Chain length: 1
Device Id: 00000111000001100100000011011101 (0x070640DD)
Manufacturer: Altera (0x0DD)
Part(0): EPM7064S (0x7064)
I created the SVF file with Altera Quartus II, but when I try to upload to the CPLD this happens:
jtag> svf verilog-test.svf progress stop
requested frequency 100000, now calibrating delay loop
new real frequency 299977, delay 1
new real frequency 301360, delay 2
new real frequency 300062, delay 6
new real frequency 296239, delay 18
new real frequency 287286, delay 53
new real frequency 285188, delay 152
new real frequency 261689, delay 433
new real frequency 220446, delay 1133
new real frequency 169987, delay 2497
new real frequency 128723, delay 4244
new real frequency 112857, delay 5462
new real frequency 103550, delay 6164
warning: unimplemented mode 'ABSENT' for TRST
Error svf: mismatch at position 27 for TDO
in input file between line 66 col 1 and line 66 col 54
error: Error occurred for SVF command, line 65, column 0-53:
detail: Parsing 25400/25403 ( 99%)detail:
detail: Mismatches occurred between scanned device output and expected TDO values.
I've been told I can safely ignore the warning but haven't found anything useful regarding the SVF error.
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