Hello,

I am trying to use urJTAG to do dynamic configuration of an Altera StratixV FPGA using an SVF file. urJTAG can do this, it does work. The problem is it takes a very long time, 30 minutes at least, to parse the SVF file. The SVF file is 53 MB. The long configuration shift is 213798928 bits long.

I am using the Altera UsbBlaster with the ftd2xx driver. The hardware seems to perform at good speed once the parsing is finished.

Is there anything I can do to optimize the code for larger files? I used printfs to find where the code was spending the majority of the time. I narrowed down most of the processing to a do-while loop in svf_flex.c, and will include this code below. It does jump out of the loop but returns to it again and again, so that's why I say "majority of the time". I don't know what I can do from here, at least not without much in depth study of this code. Any help is greatly appreciated!

Thanks.

~~~~~~~
do
{
printf("DEBUG: svf_flex->svflex function: 4.0\n");
register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
if ( yy_accept[yy_current_state] )
{
yyg->yy_last_accepting_state = yy_current_state;
yyg->yy_last_accepting_cpos = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 43 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
++yy_cp;
}
~~~~~~

 
Last edit: Shane Gidley 2014-02-05