#108 ejtag_dma bus driver not detecting debug mode

UrJTAG (102)

This is my first post at sourceforge.
I'm currently experimenting Urjtag with a Segger SAM-ICE Jlink USB adapter and a board with Toshiba TX4939 (MIPS 64 compatible).
Urjtag is recognizing the cable and detecting the microprocessor. I am actually using Toshiba TX4925 configuration renamed to TX4939. Even though they are not pin compatible, their EJTAG is 100% compatible. When I try to initialize the bus, it prints an error message. Below the sequence of commands and responses:

claudio@clau2:~/Desktop/dnld/urjtag-0.10$ sudo jtag

UrJTAG 0.10 #1502
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

WARNING: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable jlink
J-Link initial read failed, don't worry (result=-110)
Vref = 2.329 TCK=1 TDI=0 TDO=0 TMS=0 TRES=1 TRST=1
J-Link JTAG Interface ready
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00010000000000111111000000110001 (0x000000001003F031)
Manufacturer: Toshiba
Part(0): TX4939
Stepping: 1
Filename: /usr/local/share/urjtag/toshiba/tx4939/tx4939

jtag> initbus ejtag_dma
EJTAG version: <= 2.0
EJTAG Implementation flags: R4k DMA MIPS64
chain.c(149) Part 0 without active instruction
ejtag_dma.c(431) Failed to enter debug mode, ctrl=00000000001000001000000110001000
bus initialization failed!

The code that generated that error message is in urjtag-0.10/src/bus/ejtag_dma.c:

/* Wait until processor is in break */
ejctrl->in->data[JtagBrk] = 0;
do {
chain_shift_data_registers( CHAIN, 1 );
if (!timeout) break;
} while ( ejctrl->out->data[BrkSt] == 1 );

if (timeout == 0)
printf( _("%s(%d) Failed to enter debug mode, ctrl=%s\n"),
__FILE__, __LINE__,
register_get_string( ejctrl->out ) );

The code writes a ZERO to JtagBrk and wait till BrkSt is ZERO. Looking at MIPS EJTAG specification, I saw that both are inverted:
( DM = debug mode )
EjtagBrk Requests a Debug Interrupt exception to the processor
when this bit is written as 1. The debug exception
request is ignored if the processor is already in debug at
the time of the request. A write of 0 is ignored.

DM Indicates if the processor is in Debug Mode:
Encoding Meaning
0 Processor is not in Debug Mode
1 Processor is in Debug Mode

Till the end of this week I will check if this was the cause of the error message. I'm also having a problem with the ejtag (different from ejtag_dma), that I intend to check.


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