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In this first release, all of the uRISC instructions are implemented, although the code is not commented nor easily understandable. Besides, there is a known bug, which is not planned to be corrected as soon as we have our first Verilog implementation released.
uRISC is a 16-bit RISC processor projected by the associate professor at Federal University of Minas Gerais, Claudionor Coelho.
http://www.lecom.dcc.ufmg.br/urisc/urisc.html

New course, new teacher, new staff, new language.
Now, we must descript uRISC in Verilog HDL.

uRISC is a simple 16-bit RISC core processor, specified by Dr. Coelho, associate professor at Federal University of Minas Gerais.

http://www.lecom.dcc.ufmg.br/urisc/urisc.html (Portuguese)

Wait soon for a Verilog description of uRISC.

Hello, fellows.

This is our first release. Based on the proposal at our text book, we've implemented a functional emulator for MIPS. It may work under 32-bits machines. The assembler should work only for little-endian 32-bit machines.
We are promising docs for the next release, and a soon release for the uRISC implementation. Its specification will be translated and submitted as a doc.

Regards.