Port binding by implicit order in Verilog importer

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#61 Port binding by implicit order in Verilog importer

Status: open

Owner: Neil Steiner

Labels: Functionality (29)

Priority: 5

Updated: 2013-06-11

Created: 2013-06-11

Private: No

The structural Verilog importer only supports port binding by name at present. Should extend this to include binding by implicit port order.