I have a 18F46K80 and have eusart1 working fine at 115k, I have used the "Dan_tinybld18F25K80....16Mhz_19200" file as a template and changed the xtal to 40000000 and also changed the SELECTEUSART to "2" but i cannot get eusart2 to work. Perhaps something on those pins needs to be disabled such as PSP ? Again, eusart1 works fine. I changed to pins 29 and 30 as well. Thanks!
radix DEC
; change these lines accordingly to your application
include "p18f46k80.inc"
IdTypePIC = 0x66 ; Please refer to the table below, must exists in "piccodes.ini"
define max_flash 0x10000 ; in WORDS, not bytes!!! (= 'max flash memory' from "piccodes.ini" divided by 2), Please refer to the table below
define SELECTEUSART 2 ; EUSART(1/2), Please refer to the table below
xtal EQU 40000000 ; you may also want to change: _HS_OSC _XT_OSC
baud EQU 115200 ; standard TinyBld baud rates: 115200 or 19200
; The above 6 lines can be changed and buid a bootloader for the desired frequency (and PIC type)
;********************************************************************;TinyBootloader18F2XK80/18F4XK80/18F6XK80Size=100words;claudiu.chiculita@ugal.ro;http://www.etc.ugal.ro/cchiculita/software/picbootloader.htm;;ThisprogramisonlyavailableinTinyAVR/PICBootloader+.;;TinyAVR/PICBootloader+;https://sourceforge.net/projects/tinypicbootload/;;********************************************************************#include"spbrgselect.inc" ; RoundResult and baud_rate#define first_address max_flash-200 ;100 words
; PIC18F46K80 Configuration Bit Settings
; ASM source line config statements
; CONFIG1L
CONFIG RETEN = OFF ; VREG Sleep Enable bit (Ultra low-power regulator is Disabled (Controlled by REGSLP bit))
CONFIG INTOSCSEL = HIGH ; LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
CONFIG SOSCSEL = HIGH ; SOSC Power Selection and mode Configuration bits (High Power SOSC circuit selected)
CONFIG XINST = OFF ; Extended Instruction Set (Disabled)
; CONFIG1H
CONFIG FOSC = EC3 ; Oscillator (EC oscillator (High power, 16 MHz - 64 MHz))
CONFIG PLLCFG = OFF ; PLL x4 Enable bit (Disabled)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor (Disabled)
CONFIG IESO = OFF ; Internal External Oscillator Switch Over Mode (Disabled)
; CONFIG2L
CONFIG PWRTEN = OFF ; Power Up Timer (Disabled)
CONFIG BOREN = OFF ; Brown Out Detect (Disabled in hardware, SBOREN disabled)
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (1.8V)
CONFIG BORPWR = LOW ; BORMV Power level (BORMV set to low power level)
; CONFIG2H
CONFIG WDTEN = OFF ; Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
CONFIG WDTPS = 1 ; Watchdog Postscaler (1:1)
; CONFIG3H
CONFIG CANMX = PORTB ; ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)
CONFIG MSSPMSK = MSK7 ; MSSP address masking (7 Bit address masking mode)
CONFIG MCLRE = ON ; Master Clear Enable (MCLR Enabled, RE3 Disabled)
;view with TabSize=4
;&&&&&&&&&&&&&&&&&&&&&&& START &&&&&&&&&&&&&&&&&&&&&&
;---------------------- Bootloader ----------------------
;PC_flash: C1h U H L 64 ... <64 bytes> ... crc
;PC_eeprom: C1h 40h EEADRH EEADR 1 EEDATA crc
;PC_cfg C1h U OR 80h H L 14 ... <14 bytes> ... crc
;PIC_response: type K
ORG first_address ;space to deposit first 4 instr. of user prog.
nop
nop
nop
nop
org first_address+8
IntrareBootloader:
;skip TRIS to 0 C6
bsf OSCCON,IRCF0 ;int clock 16MHz
movlw ((1<<TXEN) | (1<<BRGH)) ;init serial port
movwf _TXSTA
;use only SPBRG (8 bit mode default) not using BAUDCON
movlw spbrg_value
movwf _SPBRG
movlw ((1<<SPEN) | (1<<CREN))
movwf _RCSTA
;wait for computer
rcall Receive
sublw 0xC1 ;Expect C1h
bnz way_to_exit
movlw IdTypePIC ;send PIC type
movwf _TXREG
rcall Receive ;count
movwf i
movwf count
clrf FSR0L ;FSR0=buffer TOP
rcvoct: ;read 64 bytes
rcall Receive
movwf POSTINC0
movwf TABLAT ;prepare for cfg; => store byte before crc
movwf EEDATA ;(for EEPROM case)
decfsz i
bra rcvoct
rcall Receive ;get crc
ziieroare: ;CRC failed
movlw 'N'
bnz mainl
btfss flag,6 ;is EEPROM data?
bra noeeprom
movlw (1<<WREN) ;Setup eeprom
rcall Write
bra waitwre
noeeprom:
clrf FSR0L ;FSR0=buffer TOP
btfss flag,7 ;is CFG data?
bra noconfig
TBLRD*- ; point to adr-1
lp_noeeprom:
rcall put1byte
rcall Write
decfsz count,f
bra lp_noeeprom
bra waitwre
noconfig:
;write
eraseloop:
movlw ((1<<EEPGD) | (1<<FREE) | (1<<WREN)) ; Setup erase
rcall Write
TBLRD*- ; point to adr-1
writebigloop:
writesloop:
writebyte:
rcall put1byte
decfsz count ; 64/128 bytes?
bra writebyte
Receive:
movlw (xtal/2000000+1) ; for 20MHz => 11 => 1second delay
movwf cnt1
rpt2:
clrf cnt2
rpt3:
clrf cnt3
rptc:
btfss PIR1,RCIF ;test RX
bra notrcv
movf _RCREG,w ;return read data in W
addwf crc,f ;compute crc
return
notrcv:
decfsz cnt3
bra rptc
decfsz cnt2
bra rpt3
decfsz cnt1
bra rpt2
;timeout:
way_to_exit:
bcf _RCSTA,SPEN ; deactivate UART
bra first_address
;*********
; After reset
; Do not expect the memory to be zero,
; Do not expect registers to be initialised like in catalog.
END
Last edit: Walter Marchewka 2015-03-20
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I have a 18F46K80 and have eusart1 working fine at 115k, I have used the "Dan_tinybld18F25K80....16Mhz_19200" file as a template and changed the xtal to 40000000 and also changed the SELECTEUSART to "2" but i cannot get eusart2 to work. Perhaps something on those pins needs to be disabled such as PSP ? Again, eusart1 works fine. I changed to pins 29 and 30 as well. Thanks!
; change these lines accordingly to your application
include "p18f46k80.inc"
IdTypePIC = 0x66 ; Please refer to the table below, must exists in "piccodes.ini"
define max_flash 0x10000 ; in WORDS, not bytes!!! (= 'max flash memory' from "piccodes.ini" divided by 2), Please refer to the table below
define SELECTEUSART 2 ; EUSART(1/2), Please refer to the table below
xtal EQU 40000000 ; you may also want to change: _HS_OSC _XT_OSC
baud EQU 115200 ; standard TinyBld baud rates: 115200 or 19200
; The above 6 lines can be changed and buid a bootloader for the desired frequency (and PIC type)
; +---------+--------+------------+------------+-------------+-------------+-----------+--------+------+
; |IdTypePIC| Device | Write_Page | Erase_Page | TX1/TX2 | RX1/RX2 | max_flash | EEPROM | PDIP |
; +---------+--------+------------+------------+-------------+-------------+-----------+--------+------+
; | 0x6C |18F25K80| 32 words | 32 words |C6(17)/B6(27)|C7(18)/B7(28)| 0x8000 | 1024 | 28 |
; | 0x6C |18F45K80| 32 words | 32 words |C6(25)/D6(29)|C7(26)/D7(30)| 0x8000 | 1024 | 40 |
; | 0x6C |18F65K80| 32 words | 32 words |G3(12)/E7(61)| G1(7)/E6(60)| 0x8000 | 1024 | 64 |
; | 0x66 |18F26K80| 32 words | 32 words |C6(17)/B6(27)|C7(18)/B7(28)| 0x10000 | 1024 | 28 |
; | 0x66 |18F46K80| 32 words | 32 words |C6(25)/D6(29)|C7(26)/D7(30)| 0x10000 | 1024 | 40 |
; | 0x66 |18F66K80| 32 words | 32 words |G3(12)/E7(61)| G1(7)/E6(60)| 0x10000 | 1024 | 64 |
; +---------+--------+------------+------------+-------------+-------------+-----------+--------+------+
#IF (SELECTEUSART == 1)
define _TXSTA TXSTA1
define _SPBRG SPBRG1
define _RCSTA RCSTA1
define _TXREG TXREG1
define _RCREG RCREG1
#ELSE
define _TXSTA TXSTA2
define _SPBRG SPBRG2
define _RCSTA RCSTA2
define _TXREG TXREG2
define _RCREG RCREG2
#ENDIF
; PIC18F46K80 Configuration Bit Settings
; ASM source line config statements
; CONFIG1L
CONFIG RETEN = OFF ; VREG Sleep Enable bit (Ultra low-power regulator is Disabled (Controlled by REGSLP bit))
CONFIG INTOSCSEL = HIGH ; LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
CONFIG SOSCSEL = HIGH ; SOSC Power Selection and mode Configuration bits (High Power SOSC circuit selected)
CONFIG XINST = OFF ; Extended Instruction Set (Disabled)
; CONFIG1H
CONFIG FOSC = EC3 ; Oscillator (EC oscillator (High power, 16 MHz - 64 MHz))
CONFIG PLLCFG = OFF ; PLL x4 Enable bit (Disabled)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor (Disabled)
CONFIG IESO = OFF ; Internal External Oscillator Switch Over Mode (Disabled)
; CONFIG2L
CONFIG PWRTEN = OFF ; Power Up Timer (Disabled)
CONFIG BOREN = OFF ; Brown Out Detect (Disabled in hardware, SBOREN disabled)
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (1.8V)
CONFIG BORPWR = LOW ; BORMV Power level (BORMV set to low power level)
; CONFIG2H
CONFIG WDTEN = OFF ; Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
CONFIG WDTPS = 1 ; Watchdog Postscaler (1:1)
; CONFIG3H
CONFIG CANMX = PORTB ; ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)
CONFIG MSSPMSK = MSK7 ; MSSP address masking (7 Bit address masking mode)
CONFIG MCLRE = ON ; Master Clear Enable (MCLR Enabled, RE3 Disabled)
; CONFIG4L
CONFIG STVREN = OFF ; Stack Overflow Reset (Disabled)
CONFIG BBSIZ = BB1K ; Boot Block Size (1K word Boot Block size)
; CONFIG5L
CONFIG CP0 = OFF ; Code Protect 00800-03FFF (Disabled)
CONFIG CP1 = OFF ; Code Protect 04000-07FFF (Disabled)
CONFIG CP2 = OFF ; Code Protect 08000-0BFFF (Disabled)
CONFIG CP3 = OFF ; Code Protect 0C000-0FFFF (Disabled)
; CONFIG5H
CONFIG CPB = OFF ; Code Protect Boot (Disabled)
CONFIG CPD = OFF ; Data EE Read Protect (Disabled)
; CONFIG6L
CONFIG WRT0 = OFF ; Table Write Protect 00800-03FFF (Disabled)
CONFIG WRT1 = OFF ; Table Write Protect 04000-07FFF (Disabled)
CONFIG WRT2 = OFF ; Table Write Protect 08000-0BFFF (Disabled)
CONFIG WRT3 = OFF ; Table Write Protect 0C000-0FFFF (Disabled)
; CONFIG6H
CONFIG WRTC = OFF ; Config. Write Protect (Disabled)
CONFIG WRTB = OFF ; Table Write Protect Boot (Disabled)
CONFIG WRTD = OFF ; Data EE Write Protect (Disabled)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protect 00800-03FFF (Disabled)
CONFIG EBTR1 = OFF ; Table Read Protect 04000-07FFF (Disabled)
CONFIG EBTR2 = OFF ; Table Read Protect 08000-0BFFF (Disabled)
CONFIG EBTR3 = OFF ; Table Read Protect 0C000-0FFFF (Disabled)
; CONFIG7H
CONFIG EBTRB = OFF ; Table Read Protect Boot (Disabled)
;----------------------------- PROGRAM ---------------------------------
cblock 0
buffer:64
crc
i
cnt1
cnt2
cnt3
flag
count
endc
;0000000000000000000000000 RESET 00000000000000000000000000
ORG 0x0000 GOTO IntrareBootloader;view with TabSize=4
;&&&&&&&&&&&&&&&&&&&&&&& START &&&&&&&&&&&&&&&&&&&&&&
;---------------------- Bootloader ----------------------
;PC_flash: C1h U H L 64 ... <64 bytes> ... crc
;PC_eeprom: C1h 40h EEADRH EEADR 1 EEDATA crc
;PC_cfg C1h U OR 80h H L 14 ... <14 bytes> ... crc
;PIC_response: type
KIntrareBootloader:
;skip TRIS to 0 C6
bsf OSCCON,IRCF0 ;int clock 16MHz
movlw ((1<<TXEN) | (1<<BRGH)) ;init serial port
movwf _TXSTA
;use only SPBRG (8 bit mode default) not using BAUDCON
movlw spbrg_value
movwf _SPBRG
movlw ((1<<SPEN) | (1<<CREN))
movwf _RCSTA
;wait for computer
rcall Receive
sublw 0xC1 ;Expect C1h
bnz way_to_exit
movlw IdTypePIC ;send PIC type
movwf _TXREG
MainLoop:
movlw 'C' ; "-Everything OK, ready and waiting."
mainl:
movwf _TXREG
clrf crc
rcall Receive ;Upper
movwf TBLPTRU
movwf flag ;(for EEPROM and CFG cases)
rcall Receive ;Hi
movwf TBLPTRH
movwf EEADRH ;(for EEPROM case)
rcall Receive ;Lo
movwf TBLPTRL
movwf EEADR ;(for EEPROM case)
rcvoct: ;read 64 bytes
rcall Receive
movwf POSTINC0
movwf TABLAT ;prepare for cfg; => store byte before crc
movwf EEDATA ;(for EEPROM case)
decfsz i
bra rcvoct
ziieroare: ;CRC failed
movlw 'N'
bnz mainl
noeeprom:
clrf FSR0L ;FSR0=buffer TOP
btfss flag,7 ;is CFG data?
bra noconfig
TBLRD*- ; point to adr-1
lp_noeeprom:
rcall put1byte
rcall Write
decfsz count,f
bra lp_noeeprom
bra waitwre
noconfig:
;write
eraseloop:
movlw ((1<<EEPGD) | (1<<FREE) | (1<<WREN)) ; Setup erase
rcall Write
TBLRD*- ; point to adr-1
writebigloop:
writesloop:
writebyte:
rcall put1byte
decfsz count ; 64/128 bytes?
bra writebyte
waitwre:
;btfsc EECON1,WR ;for eeprom writes (wait to finish write)
;bra waitwre ;no need: round trip time with PC bigger than 4ms
;* procedures *****
put1byte:
movf POSTINC0,w ; put 1 byte
movwf TABLAT
tblwt+*
retlw ((1<<EEPGD) | (1<<CFGS) | (1<<WREN)) ;Setup cfg
Write:
movwf EECON1
movlw 0x55
movwf EECON2
movlw 0xAA
movwf EECON2
bsf EECON1,WR ;WRITE
nop
;nop
return
Receive:
movlw (xtal/2000000+1) ; for 20MHz => 11 => 1second delay
movwf cnt1
rpt2:
clrf cnt2
rpt3:
clrf cnt3
rptc:
btfss PIR1,RCIF ;test RX
bra notrcv
movf _RCREG,w ;return read data in W
addwf crc,f ;compute crc
return
notrcv:
decfsz cnt3
bra rptc
decfsz cnt2
bra rpt3
decfsz cnt1
bra rpt2
;timeout:
way_to_exit:
bcf _RCSTA,SPEN ; deactivate UART
bra first_address
;*********
; After reset
; Do not expect the memory to be zero,
; Do not expect registers to be initialised like in catalog.
Last edit: Walter Marchewka 2015-03-20
Hi,Walter
Thank you very much Bug reports.
I have reviewed the program.
Register to be used for the UART is located in the all> $ F5F.
Therefore, I think the PSP configuration is the poor.
SPBRG1/2: $FAF/$F7B
RCREG1/2: $FAF/$F7A
TXREG1/2: $FAD/$F79
TXSTA1/2: $FAC/$FBA
RCSTA1/2: $FAB/$FA6
I am happy if you could tell me the results try the following.
IntrareBootloader:
;skip TRIS to 0 C6
bsf OSCCON,IRCF0 ;int clock 16MHz
--->add
LFSR 1, PMD1 ;FSR1 = PMD1
bsf INDF1,PSPMD ;disable PSP
--->add
way_to_exit:
--->add
bcf INDF1,PSPMD ; enable PSP
--->add
bcf _RCSTA,SPEN ; deactivate UART
bra first_address
Best Regards,
Dan
Dan thank you for the help. Your changes were not necessary, It was not looking at the correct interrupt for uart2, I had to change the:
btfss PIR1,RCIF ;test RX
to
btfss PIR3,RC2IF ;test RX
Thank you for your continued work on the bootloader !!!
-Walt
Hi,Walter
Thank you very much RESOLUTION.
I have to reflect the new firmware.
Best regards,
Dan