[Tinyos8051wg-commit] SF.net SVN: tinyos8051wg:[1100] trunk/diku/mcs51
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[Tinyos8051wg-commit] SF.net SVN: tinyos8051wg:[1100] trunk/diku/mcs51
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From: <mle...@us...> - 2010-01-19 19:56:59
|
Revision: 1100
http://tinyos8051wg.svn.sourceforge.net/tinyos8051wg/?rev=1100&view=rev
Author: mleopold
Date: 2010-01-19 19:56:49 +0000 (Tue, 19 Jan 2010)
Log Message:
-----------
cookie841 platform courtesy of Alfonso Martinez De La Torre
Added Paths:
-----------
trunk/diku/mcs51/support/make/cookie841.target
trunk/diku/mcs51/support/make/mcs51/cookie841.bat
trunk/diku/mcs51/tos/chips/aduc841/
trunk/diku/mcs51/tos/chips/aduc841/McuSleepC.nc
trunk/diku/mcs51/tos/chips/aduc841/README
trunk/diku/mcs51/tos/chips/aduc841/adc/
trunk/diku/mcs51/tos/chips/aduc841/adc/ADCC.nc
trunk/diku/mcs51/tos/chips/aduc841/adc/ADCControl.nc
trunk/diku/mcs51/tos/chips/aduc841/adc/Haladuc841ADCP.nc
trunk/diku/mcs51/tos/chips/aduc841/adc/adc.h
trunk/diku/mcs51/tos/chips/aduc841/aduc841hardware.h
trunk/diku/mcs51/tos/chips/aduc841/dac/
trunk/diku/mcs51/tos/chips/aduc841/dac/DACC.nc
trunk/diku/mcs51/tos/chips/aduc841/dac/DACControl.nc
trunk/diku/mcs51/tos/chips/aduc841/dac/Haladuc841DACP.nc
trunk/diku/mcs51/tos/chips/aduc841/dac/dac.h
trunk/diku/mcs51/tos/chips/aduc841/i2c/
trunk/diku/mcs51/tos/chips/aduc841/i2c/Haladuc841SimpleI2CP.nc
trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CControl.nc
trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CMaster.nc
trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CSlave.nc
trunk/diku/mcs51/tos/chips/aduc841/i2c/i2c.h
trunk/diku/mcs51/tos/chips/aduc841/ioaduc841.h
trunk/diku/mcs51/tos/chips/aduc841/pins/
trunk/diku/mcs51/tos/chips/aduc841/pins/Haladuc841LedPinP.nc
trunk/diku/mcs51/tos/chips/aduc841/pins/Hpladuc841GeneralIOC.nc
trunk/diku/mcs51/tos/chips/aduc841/pwm/
trunk/diku/mcs51/tos/chips/aduc841/pwm/Haladuc841SimplePWMP.nc
trunk/diku/mcs51/tos/chips/aduc841/pwm/PWMC.nc
trunk/diku/mcs51/tos/chips/aduc841/pwm/PWMControl.nc
trunk/diku/mcs51/tos/chips/aduc841/pwm/pwm.h
trunk/diku/mcs51/tos/chips/aduc841/spi/
trunk/diku/mcs51/tos/chips/aduc841/spi/Haladuc841SimpleSPIP.nc
trunk/diku/mcs51/tos/chips/aduc841/spi/SpiByte.nc
trunk/diku/mcs51/tos/chips/aduc841/spi/SpiControl.nc
trunk/diku/mcs51/tos/chips/aduc841/spi/spi.h
trunk/diku/mcs51/tos/chips/aduc841/timer/
trunk/diku/mcs51/tos/chips/aduc841/timer/HplAduc841Counter.nc
trunk/diku/mcs51/tos/chips/aduc841/timer/HplAduc841TimerP.nc
trunk/diku/mcs51/tos/chips/aduc841/timer/aduc841-timer.h
trunk/diku/mcs51/tos/chips/aduc841/uart/
trunk/diku/mcs51/tos/chips/aduc841/uart/Haladuc841SimpleUart0P.nc
trunk/diku/mcs51/tos/chips/aduc841/uart/SerialByteComm.nc
trunk/diku/mcs51/tos/chips/aduc841/uart/SerialControl.nc
trunk/diku/mcs51/tos/chips/aduc841/uart/serial.h
trunk/diku/mcs51/tos/platforms/cookie841/
trunk/diku/mcs51/tos/platforms/cookie841/.platform
trunk/diku/mcs51/tos/platforms/cookie841/AMReceiverC.nc
trunk/diku/mcs51/tos/platforms/cookie841/AMSenderC.nc
trunk/diku/mcs51/tos/platforms/cookie841/ActiveMessageC.nc
trunk/diku/mcs51/tos/platforms/cookie841/Aduc841Msg.h
trunk/diku/mcs51/tos/platforms/cookie841/DS18S20C.nc
trunk/diku/mcs51/tos/platforms/cookie841/HalTelegesisRadioP.nc
trunk/diku/mcs51/tos/platforms/cookie841/Haladuc841DS18S20P.nc
trunk/diku/mcs51/tos/platforms/cookie841/Haladuc841OneWireP.nc
trunk/diku/mcs51/tos/platforms/cookie841/HilTimerMilliC.nc
trunk/diku/mcs51/tos/platforms/cookie841/OneWireC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformADCC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformDACC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformDS18S20C.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformI2CC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformLedsC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformOneWireC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformP.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformPWMC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformRadioC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformSPIC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformTimerC.nc
trunk/diku/mcs51/tos/platforms/cookie841/PlatformUARTC.nc
trunk/diku/mcs51/tos/platforms/cookie841/RadioC.nc
trunk/diku/mcs51/tos/platforms/cookie841/RadioControl.nc
trunk/diku/mcs51/tos/platforms/cookie841/Send.nc
trunk/diku/mcs51/tos/platforms/cookie841/UartC.nc
trunk/diku/mcs51/tos/platforms/cookie841/hardware.h
trunk/diku/mcs51/tos/platforms/cookie841/modified/
trunk/diku/mcs51/tos/platforms/cookie841/modified/.platform
trunk/diku/mcs51/tos/platforms/cookie841/onewire.h
trunk/diku/mcs51/tos/platforms/cookie841/platform.h
trunk/diku/mcs51/tos/platforms/cookie841/platform_message.h
trunk/diku/mcs51/tos/platforms/cookie841/radio.h
Added: trunk/diku/mcs51/support/make/cookie841.target
===================================================================
--- trunk/diku/mcs51/support/make/cookie841.target (rev 0)
+++ trunk/diku/mcs51/support/make/cookie841.target 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,11 @@
+PLATFORM = cookie841
+MCS51_KEIL_SCRIPT=cookie841.bat
+
+ifdef PLATFORM
+PFLAGS += -D__$(PLATFORM)__=1
+endif
+
+$(call TOSMake_include_platform,mcs51)
+
+cookie841: $(BUILD_DEPS)
+ @:
Added: trunk/diku/mcs51/support/make/mcs51/cookie841.bat
===================================================================
--- trunk/diku/mcs51/support/make/mcs51/cookie841.bat (rev 0)
+++ trunk/diku/mcs51/support/make/mcs51/cookie841.bat 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,21 @@
+echo off
+SET C51INC=C:\Keil\C51\INC\ADI\;C:\Keil\C51\INC\
+SET C51LIB=C:\Keil\C51\LIB
+SET CPU_TYPE=ADUC841
+SET CPU_VENDOR=Analog Devices, Inc.
+SET UV2_TARGET=Target 1
+SET CPU_XTAL=0x016E3600
+echo on
+
+rem Compile app.c to app.obj
+C:\Keil\C51\BIN\C51.EXE "app.c" BROWSE DEBUG OBJECTEXTEND LARGE CODE LISTINCLUDE SYMBOLS PRINT(.\app.lst) OBJECT(.\app.obj)
+
+rem Link startup.obj/app.obj and convert to hex
+C:\Keil\C51\BIN\BL51.EXE "startup.obj", "app.obj" TO "app" PRINT (app.map) CODE(0-0xFBFF) RAMSIZE (256) XDATA (0X0000-0X07FF) REGFILE(app.reg)
+C:\Keil\C51\BIN\OH51.EXE "app"
+
+rem Link using LX51 which should contain some optimisations...
+rem LX51 is only available in the "professional edition"
+C:\Keil\C51\BIN\LX51.EXE "startup.obj", "app.obj" TO "app" PRINT (app.map) CLASSES( XDATA(X:0x0000-X:0x0FFF), IDATA(I:0-I:0xFF)) REGFILE(app.reg)
+C:\Keil\C51\BIN\OHX51.EXE "app"
+
Added: trunk/diku/mcs51/tos/chips/aduc841/McuSleepC.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/McuSleepC.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/McuSleepC.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2007 University of Copenhagen
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of University of Copenhagen nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY
+ * OF COPENHAGEN OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *
+ * Dummy sleep mode for 8051
+ *
+ * @author Martin Leopold <le...@di...>
+ */
+
+ /**
+ * @modified Yana E. Krasteva <yan...@up...>
+ *for ADUC841
+ */
+
+
+
+#include "aduc841hardware.h"
+#include "ioaduc841.h"
+
+module McuSleepC {
+ provides {
+ interface McuSleep;
+ interface McuPowerState;
+ }
+}
+implementation {
+
+ async command void McuSleep.sleep() {
+ // Allow interrupts to squize in... (See TEP112)
+ __nesc_enable_interrupt();
+ {uint8_t q=0;
+ while(q<10) {
+ q++;
+ }
+ //__nesc_enable_interrupt();
+ //SBUF='A';
+ }
+ __nesc_disable_interrupt();
+ }
+
+ async command void McuPowerState.update() {
+ }
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/README
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/README (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/README 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,4 @@
+Analog Devices 8051 base
+======================
+
+Common ancestor of the Analog Device 8051 (www.analog.com)
Added: trunk/diku/mcs51/tos/chips/aduc841/adc/ADCC.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/adc/ADCC.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/adc/ADCC.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,15 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <adc.h>
+
+interface ADCC {
+
+ async command uint16_t getData();
+
+ async command uint8_t getChannel();
+
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/adc/ADCControl.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/adc/ADCControl.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/adc/ADCControl.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,32 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <adc.h>
+
+interface ADCControl {
+
+ /**
+ * Set ADC mode
+ *
+ * @param mode mode flags as defined in adc.h
+ */
+
+ command error_t setMode(type_power mode);
+ command error_t setRef(type_ref ref);
+ command error_t setCLKDivison(type_div di);
+ command error_t setAcq(type_acq acq);
+ command error_t enableT2C();
+ command error_t disableT2C();
+ command error_t enableEXC();
+ command error_t disableEXC();
+ async command error_t enableCCONV();
+ async command error_t disableCCONV();
+ async command error_t enableSCONV();
+ command error_t enableDMA();
+ command error_t setChannel(type_cha channel);
+
+
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/adc/Haladuc841ADCP.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/adc/Haladuc841ADCP.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/adc/Haladuc841ADCP.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,168 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <ioaduc841.h>
+#include <adc.h>
+
+module Haladuc841ADCP {
+ provides interface ADCC;
+ provides interface ADCControl;
+ provides interface StdControl;
+ provides interface Init;
+
+
+} implementation {
+
+ error_t a;
+
+ command error_t Init.init(){
+
+ ADCCON1 = 0x00;
+ ADCCON2 = 0x00;
+ ADCCON3 = 0x00;
+ a = call StdControl.start();
+ return (a);
+ }
+
+ command error_t StdControl.stop() {
+ ADCCON1 &= 0x7F;
+ return SUCCESS;
+ }
+
+ command error_t StdControl.start() {
+
+ call ADCControl.setMode(ADC_POWER_UP);
+ call ADCControl.setCLKDivison(ADC_CLK_DIV_8);
+ call ADCControl.setAcq(ADC_ACQ_4);
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.setMode(type_power new_mode) {
+ atomic {
+ ADCCON1 &= 0x7F;
+ ADCCON1 |= new_mode;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.setRef(type_ref new_ref){
+ atomic {
+ ADCCON1 &= 0xBF;
+ ADCCON1 |= new_ref;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.setCLKDivison(type_div new_div){
+ atomic {
+ ADCCON1 &= 0xCF;
+ ADCCON1 |= new_div;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.setAcq(type_acq new_acq){
+ atomic {
+ ADCCON1 &= 0xF3;
+ ADCCON1 |= new_acq;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.enableT2C(){
+ atomic {
+ ADCCON1 |= 0x02;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.disableT2C(){
+ atomic {
+ ADCCON1 &= 0xFD;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.enableEXC(){
+ atomic {
+ ADCCON1 |= 0x01;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.disableEXC(){
+ atomic {
+ ADCCON1 &= 0xFE;
+ }
+ return SUCCESS;
+ }
+
+ async command error_t ADCControl.enableCCONV(){
+ atomic {
+ ADCCON2 |= 0x20;
+ }
+ return SUCCESS;
+ }
+
+ async command error_t ADCControl.disableCCONV(){
+ atomic {
+ ADCCON2 &= 0xDF;
+ }
+ return SUCCESS;
+ }
+
+ async command error_t ADCControl.enableSCONV(){
+ atomic {
+ ADCCON2 |= 0x10;
+
+ while (ADCCON2 & 0x10) {}
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.enableDMA(){
+ atomic {
+ ADCCON2 |= 0x40;
+ }
+ return SUCCESS;
+ }
+
+ command error_t ADCControl.setChannel(type_cha new_channel){
+
+ atomic {
+ ADCCON2 &= 0xF0;
+ ADCCON2 |= new_channel;
+ }
+ return SUCCESS;
+ }
+
+
+
+ async command uint16_t ADCC.getData() {
+ uint16_t data;
+ atomic {
+ EADC=0;
+ data = ADCDATAH & 0x0F;
+ data = data << 8;
+ data |= ADCDATAL;
+ ADCI=0;
+ EADC=1;
+ }
+ return(data);
+ }
+
+
+ async command uint8_t ADCC.getChannel() {
+ uint8_t ch;
+ ch = ADCDATAH & 0xF0;
+ ch = ch >> 4;
+ return(ch);
+ }
+
+
+
+}
+
Added: trunk/diku/mcs51/tos/chips/aduc841/adc/adc.h
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/adc/adc.h (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/adc/adc.h 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,53 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+
+#ifndef _H_ADC_H
+#define _H_ADC_H
+
+/**
+ * Bit numbers for adc
+ */
+typedef enum {
+ ADC_EXT_REF = 0x40,
+ ADC_INT_REF = 0x00
+} type_ref;
+typedef enum {
+ ADC_POWER_UP = 0x80,
+ ADC_POWER_DOWN = 0x00
+} type_power;
+typedef enum {
+ ADC_CLK_DIV_32 = 0x00,
+ ADC_CLK_DIV_8 = 0x20,
+ ADC_CLK_DIV_4 = 0x10,
+ ADC_CLK_DIV_2 = 0x30
+} type_div;
+typedef enum {
+ ADC_ACQ_1 = 0x00,
+ ADC_ACQ_2 = 0x04,
+ ADC_ACQ_3 = 0x08,
+ ADC_ACQ_4 = 0x0C
+} type_acq;
+typedef enum {
+ ADC_CHA_0 = 0x00,
+ ADC_CHA_1 = 0x01,
+ ADC_CHA_2 = 0x02,
+ ADC_CHA_3 = 0x03,
+ ADC_CHA_4 = 0x04,
+ ADC_CHA_5 = 0x05,
+ ADC_CHA_6 = 0x06,
+ ADC_CHA_7 = 0x07,
+ ADC_CHA_TEMP_MON = 0x08,
+ ADC_CHA_DAC0 = 0x09,
+ ADC_CHA_DAC1 = 0x0A,
+ ADC_CHA_AGND = 0x0B,
+ ADC_CHA_VREF = 0x0C,
+ ADC_CHA_DIS_DMA = 0x0F
+} type_cha;
+
+
+#endif _H_ADC_H
+
Added: trunk/diku/mcs51/tos/chips/aduc841/aduc841hardware.h
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/aduc841hardware.h (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/aduc841hardware.h 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2007 University of Copenhagen
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of University of Copenhagen nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY
+ * OF COPENHAGEN OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *
+ * Ported to 8051 by Martin Leopold, Sidsel Jensen & Anders Egeskov Petersen,
+ * Dept of Computer Science, University of Copenhagen
+ *
+ * @author Martin Leopold <le...@di...>
+ * @author Sidsel Jensen,
+ * @authro Anders Egeskov Petersen
+ */
+
+
+#ifndef _H_aduc841hardware_H
+#define _H_aduc841hardware_H
+
+#include <ioaduc841.h>
+// At some point someone is probably going to use these from avrlibc =]
+
+#ifndef _BV
+#define _BV(bit) (1 << (bit))
+#endif
+
+// Borrow these from atm128hardware
+// Using these for IO seems rather silly as IO ports are bit accessible as
+// Px_y (where x is the port and y is the pin)
+#define SET_BIT(port, bit) ((port) |= _BV(bit))
+#define CLR_BIT(port, bit) ((port) &= ~_BV(bit))
+#define READ_BIT(port, bit) (((port) & _BV(bit)) != 0)
+#define FLIP_BIT(port, bit) ((port) ^= _BV(bit))
+
+// Define the input/output direction of the Px_DIR registers
+// this is the classic 8051 implementation, some variants
+// have other definitions
+
+#define MAKE_IO_PIN_OUTPUT(dir_reg, pin) dir_reg |= _BV(pin)
+#define MAKE_IO_PIN_INPUT(dir_reg, pin) dir_reg &= ~_BV(pin)
+
+// Test whether an IO pin is set to input or output
+#define IS_IO_PIN_OUTPUT(dir_reg, pin) dir_reg | _BV(pin)
+#define IS_IO_PIN_INPUT(dir_reg, pin) !(dir_reg & _BV(pin))
+
+/*
+ * We need slightly different defs than SIGNAL, INTERRUPT
+ * See gcc manual for explenation of gcc-attributes
+ * See nesC Language Reference Manual for nesc attributes
+ *
+ * signal: Interrupts are disabled inside function.
+ * interrupt: Sets up interrupt vector, but doesn't disable interrupts
+ * spontaneous: nesc attribute to indicate that there are "inisible" calls to this
+ * function i.e. interrupts
+
+ * It seems that 8051 compilers only define the interrupt keyword (not
+ * signal). It is unclear wether interrupts are disabled or enabled by
+ * default.
+
+ * We use AVR-like syntax so the mangle script looks for something like:
+ * void __vector_9() __attribute((interrupt))) {
+ *
+ * Which is mangled to
+ * void __vector interrupt 9 () {
+ *
+ * NOTE: This means that the interrupt number is passed as part of the
+ * name - so don't change it! This name is further passed to the
+ * CIL-inliner script in order for it to leave it there.
+ */
+
+// Interrupt: interrupts are enabled (probably =)
+#define ADUC841_INTERRUPT(signame) \
+void signame() __attribute((interrupt, spontaneous, C))
+
+// atomic statement runtime support
+typedef uint8_t __nesc_atomic_t;
+
+inline void __nesc_disable_interrupt() { EA=0; }
+inline void __nesc_enable_interrupt() { EA=1; }
+
+inline __nesc_atomic_t __nesc_atomic_start(void) __attribute((spontaneous)) {
+ __nesc_atomic_t tmp = EA;
+ EA = 0;
+ return tmp;
+}
+
+inline void __nesc_atomic_end(__nesc_atomic_t oldSreg) __attribute__((spontaneous)) {
+ EA = oldSreg;
+}
+
+#endif //_H_aduc841hardware_H
Added: trunk/diku/mcs51/tos/chips/aduc841/dac/DACC.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/dac/DACC.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/dac/DACC.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,16 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <dac.h>
+
+interface DACC {
+
+
+ async command error_t writeDataDAC0(uint16_t data);
+
+ async command error_t writeDataDAC1(uint16_t data);
+
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/dac/DACControl.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/dac/DACControl.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/dac/DACControl.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,40 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <dac.h>
+
+interface DACControl {
+
+ /**
+ * Set DAC mode
+ *
+ * @param mode mode flags as defined in dac.h
+ */
+
+ command error_t setMode(uint8_t mode);
+
+ command error_t setRangeDAC1(uint8_t rng1);
+
+ command error_t setRangeDAC0(uint8_t rng0);
+
+ command void setDAC0to0();
+
+ command void setDAC1to0();
+
+ command void setDAC0toV();
+
+ command void setDAC1toV();
+
+ command void PowerOnDAC0();
+
+ command void PowerOffDAC0();
+
+ command void PowerOnDAC1();
+
+ command void PowerOffDAC1();
+
+
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/dac/Haladuc841DACP.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/dac/Haladuc841DACP.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/dac/Haladuc841DACP.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,148 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <ioaduc841.h>
+#include <dac.h>
+
+module Haladuc841DACP {
+ provides interface DACC;
+ provides interface DACControl;
+ provides interface StdControl;
+ provides interface Init;
+
+
+} implementation {
+
+ error_t a;
+
+ command error_t Init.init(){
+
+ DACCON = 0x1C;
+ ADCCON1 = 0x80;
+ a = call StdControl.start();
+ return (a);
+ }
+
+ command error_t StdControl.stop() {
+ call DACControl.PowerOffDAC0();
+ call DACControl.PowerOffDAC1();
+ return SUCCESS;
+ }
+
+ command error_t StdControl.start() {
+
+ call DACControl.setMode(DAC_MODE_12);
+ call DACControl.setRangeDAC0(DAC_RNG_0_VREF);
+ call DACControl.setRangeDAC1(DAC_RNG_1_VREF);
+ call DACControl.PowerOnDAC0();
+ call DACControl.PowerOnDAC1();
+ return SUCCESS;
+ }
+
+ command error_t DACControl.setMode(uint8_t new_mode) {
+ atomic {
+ DACCON &= 0x7F;
+ DACCON |= new_mode;
+ }
+ return SUCCESS;
+ }
+
+ command error_t DACControl.setRangeDAC1(uint8_t new_rng1){
+ atomic {
+ DACCON &= 0xBF;
+ DACCON |= new_rng1;
+ }
+ return SUCCESS;
+ }
+
+ command error_t DACControl.setRangeDAC0(uint8_t new_rng0){
+ atomic {
+ DACCON &= 0xDF;
+ DACCON |= new_rng0;
+ }
+ return SUCCESS;
+ }
+
+ command void DACControl.setDAC0to0(){
+ atomic {
+ DACCON &= 0xF7;
+ }
+ }
+
+ command void DACControl.setDAC1to0(){
+ atomic {
+ DACCON &= 0xEF;
+ }
+ }
+
+ command void DACControl.setDAC0toV(){
+ atomic {
+ DACCON |= 0x08;
+ }
+ }
+
+ command void DACControl.setDAC1toV(){
+ atomic {
+ DACCON |= 0x10;
+ }
+ }
+
+ command void DACControl.PowerOnDAC0(){
+ atomic {
+ DACCON |= 0x01;
+ }
+ }
+
+ command void DACControl.PowerOnDAC1(){
+ atomic {
+ DACCON |= 0x02;
+ }
+ }
+
+ command void DACControl.PowerOffDAC0(){
+ atomic {
+ DACCON &= 0xFE;
+ }
+ }
+
+ command void DACControl.PowerOffDAC1(){
+ atomic {
+ DACCON &= 0xFD;
+ }
+ }
+
+ async command error_t DACC.writeDataDAC0(uint16_t data) {
+ atomic DACCON &= 0xFB;
+ if ((DACCON & 0x80) == 0x00) {
+ DAC0L=data&0x00FF;
+ DAC0H=(data>>8)&0x000F;
+ }
+ else {
+ DAC0L=data&0x00FF;
+ }
+ atomic DACCON |= 0x04;
+ return SUCCESS;
+ }
+
+ async command error_t DACC.writeDataDAC1(uint16_t data) {
+ atomic DACCON &= 0xFB;
+ if ((DACCON & 0x80) == 0x00) {
+ DAC1L=data&0x00FF;
+ DAC1H=(data>>8)&0x000F;
+ }
+ else {
+ DAC1L=data&0x00FF;
+ }
+ atomic DACCON |= 0x04;
+ return SUCCESS;
+ }
+
+
+
+
+
+}
+
Added: trunk/diku/mcs51/tos/chips/aduc841/dac/dac.h
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/dac/dac.h (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/dac/dac.h 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,25 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+
+#ifndef _H_DAC_H
+#define _H_DAC_H
+
+/**
+ * Bit numbers for dac
+ */
+enum {
+ DAC_MODE_8 = 0x80,
+ DAC_MODE_12 = 0x00,
+ DAC_RNG_1_VDD = 0x40,
+ DAC_RNG_1_VREF = 0x00,
+ DAC_RNG_0_VDD = 0x20,
+ DAC_RNG_0_VREF = 0x00
+};
+
+
+#endif _H_DAC_H
+
Added: trunk/diku/mcs51/tos/chips/aduc841/i2c/Haladuc841SimpleI2CP.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/i2c/Haladuc841SimpleI2CP.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/i2c/Haladuc841SimpleI2CP.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,350 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <ioaduc841.h>
+#include <i2c.h>
+
+module Haladuc841SimpleI2CP {
+ provides interface I2CMaster;
+ provides interface I2CSlave;
+ provides interface I2CControl;
+ provides interface StdControl;
+ provides interface Init;
+
+
+} implementation {
+
+ uint8_t mode, buf;
+ error_t a;
+
+ command error_t StdControl.stop() {
+ IEIP2&=0xFE; // Disable I2C interrupt
+ call I2CControl.disableI2C();
+ return SUCCESS;
+ }
+
+ command error_t StdControl.start() {
+ call I2CControl.setMode(mode);
+ IEIP2|=0x01; // Enable I2C interrupt
+ call I2CControl.enableI2C();
+ MDE=1;
+ MDI=0;
+ return SUCCESS;
+ }
+
+ command error_t I2CControl.setMode(uint8_t new_mode) {
+
+ atomic {
+ I2CCON &= 0xF7;
+ I2CCON |= new_mode;
+ }
+ return SUCCESS;
+ }
+
+ command error_t I2CControl.enableI2C() {
+ atomic SPE = 0; // Enable I2C
+ return SUCCESS;
+ }
+
+ command error_t I2CControl.disableI2C(){
+ atomic SPE = 1; // Disable I2C
+ return SUCCESS;
+ }
+
+ command error_t Init.init(){
+ mode = I2C_MASTER;
+
+ a = call StdControl.start();
+ return (a);
+
+ }
+
+
+
+ async command void I2CMaster.sendADD( uint8_t ADD ) {
+ uint8_t i;
+ uint8_t p = 0;
+
+
+ atomic {
+ for(i=0;i<7;i++)
+ {
+ if((ADD&0x80)==0)
+ MDO = 0;
+ else
+ MDO = 1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO = 1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO = 0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ ADD<<=1;
+
+ }
+ MDO=0;
+ }
+ }
+
+ async command void I2CMaster.sendDAT( uint8_t DAT ) {
+ uint8_t i;uint8_t p = 0;
+ atomic {
+ for(i=0;i<8;i++)
+ {
+ MDO=(DAT>>(7-i))&0x01;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO = 1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO = 0;
+
+ }
+ MDO=0;
+
+ }
+ }
+
+ default async event void I2CSlave.sendDAT() {
+ atomic {
+ I2CGC=0;
+ I2CDAT=buf;
+ }
+ }
+
+ default async event void I2CSlave.readDAT() {
+ atomic I2CGC=0;
+ atomic buf=I2CDAT;
+ }
+
+
+
+ async command uint8_t I2CSlave.readRW() {
+ uint8_t data = 0x00;
+ data = I2CTX;
+ atomic I2CTX = 0;
+ return(data);
+ }
+
+
+
+
+ async command uint8_t I2CMaster.readDAT() {
+ uint8_t p = 0;
+ uint8_t i,data;
+ atomic {
+ MDE=0;
+ data=0x00;
+ for(i=0;i<8;i++)
+ {
+ MCO = 1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ data<<=1;
+ if(MDI)
+ data |=1;
+
+ MCO = 0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ }
+ MDE=1;
+ }
+ return data;
+ }
+
+ async command error_t I2CMaster.sendSimpleData( uint8_t ADD, uint8_t DAT) {
+ call I2CMaster.sendSTART();
+ call I2CMaster.sendADD(ADD);
+ call I2CMaster.sendWRITE();
+ if (call I2CMaster.readACK()){
+ call I2CMaster.sendDAT(DAT);
+ }
+ call I2CMaster.sendSTOP();
+ return SUCCESS;
+ }
+
+ async command uint8_t I2CMaster.readSimpleData( uint8_t ADD) {
+ uint8_t b;
+ call I2CMaster.sendSTART();
+ call I2CMaster.sendADD(ADD);
+ call I2CMaster.sendREAD();
+ if (call I2CMaster.readACK()){
+ b = call I2CMaster.readDAT();
+ }
+ call I2CMaster.sendSTOP();
+ return b;
+ }
+
+
+ async command void I2CMaster.sendSTART() {
+ uint8_t p = 0;
+ atomic {
+ MDO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MDO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ }
+ }
+
+ async command void I2CMaster.sendSTOP() {
+ uint8_t p = 0;
+ atomic {
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MDO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MDO=0;
+ }
+ }
+
+ async command void I2CMaster.sendREAD() {
+ uint8_t p = 0;
+ atomic {
+ MDO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MDO=0;
+ }
+ }
+ async command void I2CMaster.sendWRITE() {
+ uint8_t p = 0;
+ atomic {
+ MDO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ }
+ }
+ async command bool I2CMaster.readACK() {
+ uint8_t p = 0;
+ atomic {
+ MDE=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MDE=1;
+ }
+ if (MDI==0) p=1;
+ return (p);
+ }
+
+ async command void I2CMaster.sendACK() {
+ uint8_t p = 0;
+ atomic {
+ MDO=0;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ }
+ }
+
+ async command void I2CMaster.sendNACK() {
+ uint8_t p = 0;
+ atomic {
+ MDO=1;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ }
+
+ }
+
+ async command bool I2CMaster.readNACK() {
+ uint8_t p = 0;
+ atomic {
+ MDE=0;
+ MCO=1;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MCO=0;
+ while (p<1) {
+ p++;
+ }p = 0;
+ MDE=1;
+ }
+ if (MDI==1) p=1;
+ return (p);
+ }
+
+
+ ADUC841_INTERRUPT(SIG_SPI_I2C) {
+
+ if (!(call I2CSlave.readRW())){
+ signal I2CSlave.readDAT();
+ }
+ else {
+ signal I2CSlave.sendDAT();
+ }
+ }
+
+}
+
Added: trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CControl.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CControl.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CControl.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,23 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <i2c.h>
+
+interface I2CControl {
+
+ /**
+ * Set I2C mode
+ *
+ * @param mode mode flags as defined in i2c.h
+ */
+
+ command error_t setMode(uint8_t mode);
+
+ command error_t enableI2C();
+
+ command error_t disableI2C();
+
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CMaster.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CMaster.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CMaster.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,40 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <i2c.h>
+
+interface I2CMaster {
+
+ async command void sendADD( uint8_t ADD );
+
+ async command void sendDAT( uint8_t DAT );
+
+ async command uint8_t readDAT();
+
+ async command void sendSTART();
+
+ async command void sendSTOP();
+
+ async command void sendREAD();
+
+ async command void sendWRITE();
+
+ async command bool readACK();
+
+ async command void sendACK();
+
+ async command void sendNACK();
+
+ async command bool readNACK();
+
+ async command error_t sendSimpleData( uint8_t ADD, uint8_t DAT);
+
+ async command uint8_t readSimpleData( uint8_t ADD);
+
+
+
+
+}
Added: trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CSlave.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CSlave.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/i2c/I2CSlave.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,18 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+#include <i2c.h>
+
+interface I2CSlave {
+
+ async event void sendDAT();
+
+ async event void readDAT();
+
+ async command uint8_t readRW();
+
+
+}
\ No newline at end of file
Added: trunk/diku/mcs51/tos/chips/aduc841/i2c/i2c.h
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/i2c/i2c.h (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/i2c/i2c.h 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,20 @@
+
+/**
+ *
+ * @author Alfonso Mart\xEDnez <Alf...@ho...>
+ */
+
+
+#ifndef _H_I2C_H
+#define _H_I2C_H
+
+/**
+ * Bit numbers for I2C
+ */
+enum {
+ I2C_SLAVE = 0x00,
+ I2C_MASTER = 0x08,
+};
+
+#endif _H_I2C_H
+
Added: trunk/diku/mcs51/tos/chips/aduc841/ioaduc841.h
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/ioaduc841.h (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/ioaduc841.h 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2008 Polaric
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Polaric nor the names of its contributors may
+ * be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL POLARIC OR ITS CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @author Martin Leopold <le...@po...>
+ */
+
+
+/**
+ * @modified Yana E. Krasteva <yan...@up...>
+ * 1. elminar los registro que no existen en el adu841 -ok
+ * 2. modificar los que se repiten - ok
+ * 3. aniadir nuevos
+ */
+
+
+#ifndef _H_aduc841_H
+#define _H_aduc841_H
+
+/*
+ * Bit locations for SCON
+ */
+
+
+enum {
+ aduc841_SCON_S0MODE = 0x7,
+ aduc841_SCON_MCE0 = 0x5,
+ aduc841_SCON_REN0 = 0x4,
+ aduc841_SCON_TB80 = 0x3,
+ aduc841_SCON_RB80 = 0x2,
+ aduc841_SCON_TI0 = 0x1,
+ aduc841_SCON_RI0 = 0x0
+};
+
+
+/*
+ * Bit locations for SPICON
+ */
+
+ /* YEK:
+ * Modificado(ADuC841 manual pagina 46)
+ */
+enum {
+ ADUC841_SPICON_ISPI = 0x7,
+ ADUC841_SPICON_WCOL = 0x6,
+ ADUC841_SPICON_SPIE = 0x5,
+ ADUC841_SPICON_SPIM = 0x4,
+ ADUC841_SPICON_CPOL = 0x3,
+ ADUC841_SPICON_CPHA = 0x2,
+ ADUC841_SPICON_SPR1 = 0x1,
+ ADUC841_SPICON_SPR0 = 0x0
+};
+
+/*
+ * Bit locations for CFG841
+ */
+
+enum {
+ ADUC841_CFG841_DIV_32 = 0x00,
+ ADUC841_CFG841_DIV_64 = 0x04,
+ ADUC841_CFG841_DIV_128 = 0x08,
+ ADUC841_CFG841_DIV_256 = 0x0C,
+ ADUC841_CFG841_DIV_512 = 0x10,
+ ADUC841_CFG841_DIV_1024 = 0x14
+};
+
+/*
+ * Bit locations for CLKMUL
+ */
+
+ /* YEK:
+ * No existe en el aduc8051
+ * codigo comentado
+ */
+
+/*
+enum {
+ ADUC841_CLKMUL_MULEN = 0x7,
+ ADUC841_CLKMUL_MULINT = 0x6,
+ ADUC841_CLKMUL_MULRDY = 0x5
+};*/
+
+/*
+ * Bit locations for IT01CF
+ */
+
+ /* YEK:
+ * No existe en el aduc8051
+ * codigo comentado
+ */
+
+/*enum {
+ ADUC841_IT01CF_IN1PL = 0x7,
+ ADUC841_IT01CF_IN0PL = 0x3,
+ ADUC841_IT01CF_IN0SL_MASK = 0x7,
+ ADUC841_IT01CF_IN1SL_MASK = 0x70
+};*/
+
+
+
+/**
+ * Special Function Register (sfr) definitions
+ */
+
+ /* YEK:
+ * Modificado(ADuC841 manual pagina 22)
+*/
+
+uint8_t volatile TMOD __attribute((sfrAT0x89));
+uint8_t volatile TL0 __attribute((sfrAT0x8A));
+uint8_t volatile TL1 __attribute((sfrAT0x8B));
+uint8_t volatile TH0 __attribute((sfrAT0x8C));
+uint8_t volatile TH1 __attribute((sfrAT0x8D));
+
+uint8_t volatile PCON __attribute((sfrAT0x87));
+uint8_t volatile TCON __attribute((sfrAT0x88));
+uint8_t volatile DPP __attribute((sfrAT0x84));//Port 2 (P2)data pointer page byte
+uint8_t volatile DPH __attribute((sfrAT0x83));
+uint8_t volatile DPL __attribute((sfrAT0x82));
+uint8_t volatile SP __attribute((sfrAT0x81));
+
+
+uint8_t volatile P1 __attribute((sfrAT0x90)); // Port 1 Latch
+uint8_t volatile I2CADD1 __attribute((sfrAT0x91));//I2C Address Register
+uint8_t volatile I2CADD2 __attribute((sfrAT0x92)); //I2C Address Register
+uint8_t volatile I2CADD3 __attribute((sfrAT0x93)); //I2C Address Register
+
+uint8_t volatile SCON __attribute((sfrAT0x98)); // UART0 Control
+uint8_t volatile SBUF __attribute((sfrAT0x99)); // UART0 Data Buffer
+uint8_t volatile I2CDAT __attribute((sfrAT0x9A)); //I2C Data Register
+uint8_t volatile I2CADD __attribute((sfrAT0x9B)); //I2C Address Register
+uint8_t volatile T3FD __attribute((sfrAT0x9D)); // Timer 3 Generated Baud Rate
+uint8_t volatile T3CON __attribute((sfrAT0x9E)); // baud rate control SFR
+
+
+uint8_t volatile P2 __attribute((sfrAT0xA0)); // Port 2 Latch
+uint8_t volatile TIMECON __attribute((sfrAT0xA1)); // Time interval counter,
+uint8_t volatile HTHSEC __attribute((sfrAT0xA2)); // Hundredths Seconds Time Register
+uint8_t volatile SEC __attribute((sfrAT0xA3)); // Seconds Time Register
+uint8_t volatile MIM __attribute((sfrAT0xA4)); // Minutes Time Register
+uint8_t volatile HOUR __attribute((sfrAT0xA5)); // Hours Time Register
+uint8_t volatile INTVAL __attribute((sfrAT0xA6)); // User Time Interval Select Register
+uint8_t volatile DPCON __attribute((sfrAT0xA7)); // DUAL DATA POINTER
+
+
+uint8_t volatile IE __attribute((sfrAT0xA8)); // Interrupt Enable
+uint8_t volatile IEIP2 __attribute((sfrAT0xA9)); // Secondary Interrupt Enable Register
+uint8_t volatile PWMCON __attribute((sfrAT0xAE)); // PULSE-WIDTH MODULATOR Control
+uint8_t volatile CFG841 __attribute((sfrAT0xAF)); // The output pins that the PWM uses are determined by the CFG841/CFG842 register
+
+
+uint8_t volatile P3 __attribute((sfrAT0xB0)); //General configuration port,
+uint8_t volatile PWM0L __attribute((sfrAT0xB1)); //PULSE-WIDTH MODULATOR VALUES
+uint8_t volatile PWM0H __attribute((sfrAT0xB2)); //PULSE-WIDTH MODULATOR VALUES
+uint8_t volatile PWM1L __attribute((sfrAT0xB3)); //PULSE-WIDTH MODULATOR VALUES
+uint8_t volatile PWM1H __attribute((sfrAT0xB4)); //PULSE-WIDTH MODULATOR VALUES
+uint8_t volatile SPH __attribute((sfrAT0xB7)); //Stack Pointer
+
+uint8_t volatile IP __attribute((sfrAT0xB8)); //Interrupt Priority
+uint8_t volatile ECON __attribute((sfrAT0xB9)); //Flash/EE Memory Control SFR
+uint8_t volatile EDATA1 __attribute((sfrAT0xBC)); //Flash/EE data
+uint8_t volatile EDATA2 __attribute((sfrAT0xBD)); //Flash/EE data
+uint8_t volatile EDATA3 __attribute((sfrAT0xBE)); //Flash/EE data
+uint8_t volatile EDATA4 __attribute((sfrAT0xBF)); //Flash/EE data
+
+uint8_t volatile WDCON __attribute((sfrAT0xC0)); //WATCHDOG TIMER
+uint8_t volatile CHIPID __attribute((sfrAT0xC2)); //
+uint8_t volatile EDARL __attribute((sfrAT0xC6)); //
+uint8_t volatile EDARH __attribute((sfrAT0xC7)); //
+
+uint8_t volatile T2CON __attribute((sfrAT0xC8)); //Timer/Counter 2 Control
+uint8_t volatile RCAP2L __attribute((sfrAT0xCA)); //Timer/Counter 2 capture/reload Low
+uint8_t volatile RCAP2H __attribute((sfrAT0xCB)); //Timer/Counter 2 capture/reload High
+uint8_t volatile TL2 __attribute((sfrAT0xCC)); //Timer/Counter 2 DATA Low
+uint8_t volatile TH2 __attribute((sfrAT0xCD)); //Timer/Counter 2 DATA High
+
+uint8_t volatile PSW __attribute((sfrAT0xD0)); //Program Status Word
+uint8_t volatile DMAL __attribute((sfrAT0xD2)); //DMA mode address pointer
+uint8_t volatile DMAH __attribute((sfrAT0xD3)); //DMA mode address pointer
+uint8_t volatile DMAP __attribute((sfrAT0xD4)); //DMA mode address pointer
+uint8_t volatile PLLCON __attribute((sfrAT0xD7)); //PLL control register
+
+uint8_t volatile ADCCON2 __attribute((sfrAT0xD8)); //ADC Control
+uint8_t volatile ADCDATAL __attribute((sfrAT0xD9)); //ADC DATA
+uint8_t volatile ADCDATAH __attribute((sfrAT0xDA)); //ADC DATA
+uint8_t volatile PSMCON __attribute((sfrAT0xDF)); //POWER SUPPLY MONITOR CONTROL
+
+
+uint8_t volatile I2CCON __attribute((sfrAT0xE8)); // I2C Control Register
+uint8_t volatile ADCCON1 __attribute((sfrAT0xEF)); // ADC conversion and acquisition time control
+
+
+uint8_t volatile B __attribute((sfrAT0xF0)); // B Register
+uint8_t volatile ADCOFSL __attribute((sfrAT0xF1)); // ADC Offset Calibration Coefficients
+uint8_t volatile ADCOFSH __attribute((sfrAT0xF2)); // ADC Offset Calibration Coefficients
+uint8_t volatile ADCGAINL __attribute((sfrAT0xF3)); // ADC Gain Calibration Coefficients
+uint8_t volatile ADCGAINH __attribute((sfrAT0xF4)); // ADC Gain Calibration Coefficients
+uint8_t volatile ADCCON3 __attribute((sfrAT0xF5)); // ADC calibration
+uint8_t volatile SPIDAT __attribute((sfrAT0xF7)); // SPI Data Register
+
+
+uint8_t volatile SPICON __attribute((sfrAT0xF8)); // SPI Control
+uint8_t volatile DAC0L __attribute((sfrAT0xF9)); // DAC Data Registers
+uint8_t volatile DAC0H __attribute((sfrAT0xFA)); // DAC Data Registers
+uint8_t volatile DAC1L __attribute((sfrAT0xFB)); // DAC Data Registers
+uint8_t volatile DAC1H __attribute((sfrAT0xFC)); // DAC Data Registers
+uint8_t volatile DACCON __attribute((sfrAT0xFD)); // DAC Control
+
+
+
+/**
+ * Bit adresseable locations
+ */
+
+ // I2CCON Slave 0xE8
+uint8_t volatile I2CSI __attribute((sbitAT0xEF));
+uint8_t volatile I2CGC __attribute((sbitAT0xEE));
+uint8_t volatile I2CID1 __attribute((sbitAT0xED));
+uint8_t volatile I2CID0 __attribute((sbitAT0xEC));
+uint8_t volatile I2CM __attribute((sbitAT0xEB));
+uint8_t volatile I2CRS __attribute((sbitAT0xEA));
+uint8_t volatile I2CTX __attribute((sbitAT0xE9));
+uint8_t volatile I2CI __attribute((sbitAT0xE8));
+
+ // IP 0xB8
+uint8_t volatile PADC __attribute((sbitAT0xBE));
+uint8_t volatile PT2 __attribute((sbitAT0xBD));
+uint8_t volatile PS __attribute((sbitAT0xBC));
+uint8_t volatile PT1 __attribute((sbitAT0xBB));
+uint8_t volatile PX1 __attribute((sbitAT0xBA));
+uint8_t volatile PT0 __attribute((sbitAT0xB9));
+uint8_t volatile PX0 __attribute((sbitAT0xB8));
+
+
+ // ADCCON2 0xD8
+uint8_t volatile ADCI __attribute((sbitAT0xDF));
+uint8_t volatile DMA __attribute((sbitAT0xDE));
+uint8_t volatile CCONV __attribute((sbitAT0xDD));
+uint8_t volatile SCONV __attribute((sbitAT0xDC));
+uint8_t volatile CS3 __attribute((sbitAT0xDB));
+uint8_t volatile CS2 __attribute((sbitAT0xDA));
+uint8_t volatile CS1 __attribute((sbitAT0xD9));
+uint8_t volatile CS0 __attribute((sbitAT0xD8));
+
+ //I2CC0N
+
+uint8_t volatile MDO __attribute((sbitAT0xEF)); // Multiprocessor Communication Enable Bit
+uint8_t volatile MDE __attribute((sbitAT0xEE)); // Receive enable
+uint8_t volatile MCO __attribute((sbitAT0xED)); // Transmit bit 8
+uint8_t volatile MDI __attribute((sbitAT0xEC)); // Receive bit 8
+uint8_t volatile I2CM __attribute((sbitAT0xEB));
+
+
+// SCON0 0x98
+uint8_t volatile SM0 __attribute((sbitAT0x9F)); // UART Serial Mode Select Bit 0
+uint8_t volatile SM1 __attribute((sbitAT0x9E)); // UART Serial Mode Select Bit 1
+uint8_t volatile SM2 __attribute((sbitAT0x9D)); // Multiprocessor Communication Enable Bit
+uint8_t volatile REN __attribute((sbitAT0x9C)); // Receive enable
+uint8_t volatile TB8 __attribute((sbitAT0x9B)); // Transmit bit 8
+uint8_t volatile RB8 __attribute((sbitAT0x9A)); // Receive bit 8
+uint8_t volatile TI __attribute((sbitAT0x99)); // Transmit interrupt flag
+uint8_t volatile RI __attribute((sbitAT0x98)); // Receive interrupt flag
+
+// IE 0xA8
+
+uint8_t volatile EA __attribute((sbitAT0xAF)); // Global interrupt enable
+uint8_t volatile EADC __attribute((sbitAT0xAE)); // Enable, or cleared to disable ADC interrupts.
+uint8_t volatile ET2 __attribute((sbitAT0xAD)); // Enable, or cleared to disable Timer 2 interrupts
+uint8_t volatile ES __attribute((sbitAT0xAC)); // UART0 interrupt enable
+uint8_t volatile ET1 __attribute((sbitAT0xAB)); // Timer1 interrupt enable
+uint8_t volatile EX1 __attribute((sbitAT0xAA)); // External interrupt 1 enable
+uint8_t volatile ET0 __attribute((sbitAT0xA9)); // Timer0 interrupt enable
+uint8_t volatile EX0 __attribute((sbitAT0xA8)); // External interrupt 0 enable
+
+
+/* TCON */
+
+uint8_t volatile TF1 __attribute((sbitAT0x8F));
+uint8_t volatile TR1 __attribute((sbitAT0x8E));
+uint8_t volatile TF0 __attribute((sbitAT0x8D));
+uint8_t volatile TR0 __attribute((sbitAT0x8C));
+uint8_t volatile IE1 __attribute((sbitAT0x8B));
+uint8_t volatile IT1 __attribute((sbitAT0x8A));
+uint8_t volatile IE0 __attribute((sbitAT0x89));
+uint8_t volatile IT0 __attribute((sbitAT0x88));
+
+
+
+
+/* P3 (0xB0) bit adressable locations */
+
+uint8_t volatile P3_0 __attribute((sbitAT0xB0));
+uint8_t volatile P3_1 __attribute((sbitAT0xB1));
+uint8_t volatile P3_2 __attribute((sbitAT0xB2));
+uint8_t volatile P3_3 __attribute((sbitAT0xB3));
+uint8_t volatile P3_4 __attribute((sbitAT0xB4));
+uint8_t volatile P3_5 __attribute((sbitAT0xB5));
+uint8_t volatile P3_6 __attribute((sbitAT0xB6));
+uint8_t volatile P3_7 __attribute((sbitAT0xB7));
+
+/* P3 (0xB0) special functions */
+uint8_t volatile RD __attribute((sbitAT0xB7)); //Read Control Signal, Logic Output. Enables the external data memory to Port 0.
+uint8_t volatile WE __attribute((sbitAT0xB6)); //Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
+uint8_t volatile T1 __attribute((sbitAT0xB5)); //Timer/Counter 1 Input.
+uint8_t volatile T0 __attribute((sbitAT0xB4)); //Timer/Counter 0 Input.
+uint8_t volatile INT1 __attribute((sbitAT0xB3)); //Interrupt 1. Programmable edge or level triggered interrupt input;
+uint8_t volatile INT0 __attribute((sbitAT0xB2)); //Interrupt 0. Programmable edge or level triggered interrupt input;
+uint8_t volatile TXD __attribute((sbitAT0xB1)); //Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of the Serial (UART) Port.
+uint8_t volatile RXD __attribute((sbitAT0xB0)); //Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of the Serial (UART) Port.
+
+/* SPIC0N (0xF8) bit adressable locations */
+
+uint8_t volatile ISPI __attribute((sbitAT0xFF)); // SPI interrupt flag
+uint8_t volatile WCOL __attribute((sbitAT0xFE)); // SPI write collision flag
+uint8_t volatile SPE __attribute((sbitAT0xFD)); // SPI Interface Enable Bit.
+uint8_t volatile SPIM __attribute((sbitAT0xFC)); // SPI Master/Slave Mode Select Bit.
+uint8_t volatile CPOL __attribute((sbitAT0xFB)); // Clock Polarity Select Bit
+uint8_t volatile CPHA __attribute((sbitAT0xFA)); // Clock Phase Select Bit.
+uint8_t volatile SPR1 __attribute((sbitAT0xF9)); // SPI Bit Rate Select Bits.
+uint8_t volatile SPR0 __attribute((sbitAT0xF8)); // SPI Bit Rate Select Bits.
+
+/* P0 bit adressable locations */
+
+uint8_t volatile P0_0 __attribute((sbitAT0x80));
+uint8_t volatile P0_1 __attribute((sbitAT0x81));
+uint8_t volatile P0_2 __attribute((sbitAT0x82));
+uint8_t volatile P0_3 __attribute((sbitAT0x83));
+uint8_t volatile P0_4 __attribute((sbitAT0x84));
+uint8_t volatile P0_5 __attribute((sbitAT0x85));
+uint8_t volatile P0_6 __attribute((sbitAT0x86));
+uint8_t volatile P0_7 __attribute((sbitAT0x87));
+
+/* P1 bit adressable locations */
+
+uint8_t volatile P1_0 __attribute((sbitAT0x90));
+uint8_t volatile P1_1 __attribute((sbitAT0x91));
+uint8_t volatile P1_2 __attribute((sbitAT0x92));
+uint8_t volatile P1_3 __attribute((sbitAT0x93));
+uint8_t volatile P1_4 __attribute((sbitAT0x94));
+uint8_t volatile P1_5 __attribute((sbitAT0x95));
+uint8_t volatile P1_6 __attribute((sbitAT0x96));
+uint8_t volatile P1_7 __attribute((sbitAT0x97));
+
+/* P2 bit adressable locations */
+uint8_t volatile P2_0 __attribute((sbitAT0xA0));
+uint8_t volatile P2_1 __attribute((sbitAT0xA1));
+uint8_t volatile P2_2 __attribute((sbitAT0xA2));
+uint8_t volatile P2_3 __attribute((sbitAT0xA3));
+uint8_t volatile P2_4 __attribute((sbitAT0xA4));
+uint8_t volatile P2_5 __attribute((sbitAT0xA5));
+uint8_t volatile P2_6 __attribute((sbitAT0xA6));
+uint8_t volatile P2_7 __attribute((sbitAT0xA7));
+
+
+/* Interrupt vector definitions */
+
+#define SIG_INT0 __vector_0 // External Interrupt 0
+#define SIG_TIMER0 __vector_1 // Timer0 Overflow
+#define SIG_INT1 __vector_2 // External Interrupt 1
+#define SIG_TIMER1 __vector_3 // Timer1 Overflow
+#define SIG_UART0 __vector_4 // Serial Port 0
+#define SIG_TIMER2 __vector_5 // Timer2 Overflow
+#define SIG_SPI __vector_6 // Serial Peripheral Interface 0
+#define SIG_SPI_I2C __vector_7 // SMBus0 Interface
+#define SIG_USB0 __vector_8 // USB Interface
+#define SIG_ADC0_WINDOW __vector_9 // ADC0 Window Comparison
+#define SIG_ADC0_EOC __vector_10 // ADC0 End Of Conversion
+#define SIG_PCA0 __vector_11 // PCA0 Peripheral
+#define SIG_COMPARATOR0 __vector_12 // Comparator0
+#define SIG_COMPARATOR1 __vector_13 // Comparator1
+#define SIG_TIMER3 __vector_14 // Timer3 Overflow
+#define SIG_VBUS_LEVEL __vector_15 // VBUS level-triggered interrupt
+#define SIG_UART1 __vector_16 // Serial Port 1
+
+
+/*PARA BORRAR EN FUTURO, CUANDO EL SISTEMA ESTE ESTABLE HAY QUE MODIFICAR LOS INTEFACES DE IO Y QUITAR ESTA VARIABLES*/
+/* P3 (0xB0) bit adressable locations */
+
+/*uint8_t volatile P0MDOUT __attribute((sbitAT0x00));
+uint8_t volatile P1MDOUT __attribute((sbitAT0x00));
+uint8_t volatile P2MDOUT __attribute((sbitAT0x00));
+uint8_t volatile P3MDOUT __attribute((sbitAT0x00));
+uint8_t volatile P0MDIN __attribute((sbitAT0x00));
+uint8_t volatile P1MDIN __attribute((sbitAT0x00));
+uint8_t volatile P2MDIN __attribute((sbitAT0x00));
+uint8_t volatile P3MDIN __attribute((sbitAT0x00));
+uint8_t volatile P0SKIP __attribute((sbitAT0x00));
+uint8_t volatile P1SKIP __attribute((sbitAT0x00));
+uint8_t volatile P2SKIP __attribute((sbitAT0x00));
+uint8_t volatile P3SKIP __attribute((sbitAT0x00));*/
+
+uint8_t volatile P0_DIR __attribute((sfrAT0xFF));
+uint8_t volatile P1_DIR __attribute((sfrAT0xFF));
+uint8_t volatile P2_DIR __attribute((sfrAT0xFF));
+
+
+
+#endif //_H_aduc841_H
Added: trunk/diku/mcs51/tos/chips/aduc841/pins/Haladuc841LedPinP.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/pins/Haladuc841LedPinP.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/pins/Haladuc841LedPinP.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2008 Polaric
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Polaric nor the names of its contributors may
+ * be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL POLARIC OR ITS CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *
+ * @author Martin Leopold <le...@po...>
+ */
+
+ /**
+ * @modified Alfonso Mart\xEDnez <Alf...@ho...>
+ * for ADUC841
+ */
+
+generic module Haladuc841LedPinP() {
+ provides {
+ interface Init;
+ interface HalMcs51Led as Led;
+ }
+ uses {
+ interface GeneralIO as Led_pin;
+ }
+}
+implementation {
+
+ /*
+ * Initialize the led to off: set the pin as output and set it
+ * high. It should also select the function of the pin by setting
+ * the P?SEL register (this is unsupported by the interface at this
+ * time).
+ */
+ command error_t Init.init() {
+ call Led_pin.makeOutput();
+ call Led_pin.set();
+ return SUCCESS;
+ }
+
+ async inline command void Led.on() {
+ call Led_pin.set();
+ }
+
+ async inline command void Led.off() {
+ call Led_pin.clr();
+ }
+
+ async inline command void Led.toggle() {
+ if(call Led_pin.get()){
+ call Led_pin.set();}
+ else {
+ call Led_pin.clr();}
+ }
+}
+
Added: trunk/diku/mcs51/tos/chips/aduc841/pins/Hpladuc841GeneralIOC.nc
===================================================================
--- trunk/diku/mcs51/tos/chips/aduc841/pins/Hpladuc841GeneralIOC.nc (rev 0)
+++ trunk/diku/mcs51/tos/chips/aduc841/pins/Hpladuc841GeneralIOC.nc 2010-01-19 19:56:49 UTC (rev 1100)
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2007 University of Copenhagen
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of University of Copenhagen nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY
+ * OF COPENHAGEN OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file is identical to HplMcs51GeneralIOC, except it adds
+ * the additional IO ports found on the ADuC841 that were not found
+ * in the classic 8051.
+ *
+ * @author Martin Leopold <le...@di...>
+ *
+ */
+
+ /*
+ * @modified Alfonso Mart\xEDnez de la Torre
+ *
+ */
+
+#include <ioaduc841.h>
+
+module Hpladuc841GeneralIOC {
+ provides interface GeneralIO as P00;
+ provides interface GeneralIO as P01;
+ provides interface GeneralIO as P02;
+ provides interface GeneralIO as P03;
+ provides interface GeneralIO as P04;
+ provides interface GeneralIO as P05;
+ provides interface GeneralIO as P06;
+ provides interface GeneralIO as P07;
+
+ provides interface GeneralIO as P10;
+ provides interface GeneralIO as P11;
+ provides interface GeneralIO as P12;
+ provides interface GeneralIO as P13;
+ provides interface GeneralIO as P14;
+ provides interface GeneralIO as P15;
+ provides interface GeneralIO as P16;
+ provides interface GeneralIO as P17;
+
+ provides interface GeneralIO as P20;
+ provides interface GeneralIO as P21;
+ provides interface GeneralIO as P22;
+ provides interface GeneralIO as P23;
+ provides interface GeneralIO as P24;
+ provides interface GeneralIO as P25;
+ provides interface GeneralIO as P26;
+ provides interface GeneralIO as P27;
+
+
+ provides interface GeneralIO as P30;
+ provides interface GeneralIO as P31;
+ provides interface GeneralIO as P32;
+ provides interface GeneralIO as P33;
+ provides interface GeneralIO as P34;
+ provides interface GeneralIO as P35;
+ provides interface GeneralIO as P36;
+ provides interface GeneralIO as P37;
+
+ provides interface Init;
+}
+
+implementation {
+#define MAKE_NEW_PIN(name, pin, pin_dir, pin_dir_bit) \
+ inline async command bool name.get() { return ( pin != 0); } \
+ inline async command void name.set() { pin = 1; } \
+ inline async command void name.clr() { pin = 0; } \
+ async command void name.toggle() { atomic { pin = ~pin; } } \
+ inline async command bool name.isInput() { IS_IO_PIN_INPUT(pin_dir, pin_dir_bit); } \
+ inline async command bool name.isOutput() { IS_IO_PIN_OUTPUT(pin_dir, pin_dir_bit); } \
+ inline async command void name.makeInput() { MAKE_IO_PIN_INPUT (pin_dir, pin_dir_bit); } \
+ inline async command void name.makeOutput() { MAKE_IO_PIN_OUTPUT(pin_dir, pin_dir_bit); }
+
+ // The syntax for defining the sbit (bit accessible registers) is
+ // compiler specfic, but the usage should be compiler independant
+
+ MAKE_NEW_PIN(P00, P0_0, P0_DIR, 0);
+ MAKE_NEW_PIN(P01, P0_1, P0_DIR, 1);
+ MAKE_NEW_PIN(P02, P0_2, P0_DIR, 2);
+ MAKE_NEW_PIN(P03, P0_3, P0_DIR, 3);
+ MAKE_NEW_PIN(P04, P0_4, P0_DIR, 4);
+ MAKE_NEW_PIN(P05, P0_5, P0_DIR, 5);
+ MAKE_NEW_PIN(P06, P0_6, P0_DIR, 6);
+ MAKE_NEW_PIN(P07, P0_7, P0_DIR, 7);
+
+ MAKE_NEW_PIN(P10, P1_0, P1_DIR, 0);
+ MAKE_NEW_PIN(P11, P1_1, P1_DIR, 1);
+ MAKE_NEW_PIN(P12, P1_2, P1_DIR, 2);
+ MAKE_NEW_PIN(P13, P1_3, P1_DIR, 3...
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