One thing I hate in Verilog HDL is implicit declaration.
I havn't found any merit of implicit declaration yet, however it sent me Hell several times.
I tried use `default_nettype none compiler derivative.
However it required to me change all 'input' to 'input wire'.
I could tell my colleague to add declarations to all wires, but I failed to change 'input' to 'input wire'. Acutally, it was very difficult to me.
Could add option to be a mimic of defined-type language in SVEditor?
I want to restrict me by below rules.
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