#528 Unary Logic Negation Operator not parsed correctly

[Scott Nixon]

Verilog code with "!" operators (reduction operator "~" also fails) gets flagged as erroneous:

For example:
if !(a) begin

"Expecting operator "(", recieved "!".

This also shows up in "iff" clauses for coverage bins.

[StevenAZ]

Can you give an example in an iff statement.

[Scott Nixon]

cp_read_write : coverpoint trans.kind iff !(a == 1'b) {
type_option.comment = "Read/Write";
bins cp_read = {READ};
bins cp_write = {WRITE};
}

[StevenAZ]

Scott, I think I am going to let Matt handle this one as he deals with LRM issues.

It doesn't look like the code above is LRM compliant, there should be braces around the (!(a==1'b1)). I'm looking at the 2012 version of the LRM, not sure if there has been an update since then that allows the code above.

[Scott Nixon]

Hah, wouldn't be the first time the simulator happily digests code that isn't LRM compatible :)

No worries, I can clean up my code to match the LRM if that is what it specifies.