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#418 Wrong beautify/formatting in systemverilog constraint block

v1.0_(example)
closed
nobody
None
5
2016-03-21
2016-03-18
No

Dear Matthew Ballance,

I have realized that there is a problem with the beautifier of SVEditor in the contraint blocks of systemverilog.
I am using Mars.2 with SVEditor 1.8.3

Here the snip to reproduce the wrong formatting

class A ; //base input transaction

//LEGAL CONSTRAINT
constraint legal_values {   
    foreach(A[j])  {
    if ((A!=0)||(B!=7)||(C!=0)) {        
    A[j] inside {[16'h0F00:16'h0F03]};        
} else {            
        A[j] >= 16'h0F00;
        B[j] + D[j] -1  <= 16'hFFFF;
    }

    //Constraint logical start_address
    A[j] >= 32'h0001_0000;
B[j] <= 32'h0002_FFFF;

foreach(A[i])  {
        if ((i!=j))   {
            A[i] > A[j]+B[j]+3; //give 3 bytes separation
            C[i] < C[j]-3; 
        }           
    } //end foreach Ii
        A[j] inside {[1:$]}
        B[j] inside {[0:7]}; 
C[j] inside {[0:7]};

} //loop           
    } //end legal values

endclass :

Please notice that i have modified the constraints and probably they are not compilable. What i wanted to show is that they are not formated correctly by the tool.
Do you know the reason?

1 Attachments

Related

Bugs: #418

Discussion

  • StevenAZ

    StevenAZ - 2016-03-19

    I will take a look at this next week Matt
    On Mar 18, 2016 7:34 AM, "Jonathan Alvarez" jonialejoniale@users.sf.net
    wrote:


    Status: open
    Group: v1.0_(example)
    Created: Fri Mar 18, 2016 02:34 PM UTC by Jonathan Alvarez
    Last Updated: Fri Mar 18, 2016 02:34 PM UTC
    Owner: nobody
    Attachments:

    Dear Matthew Ballance,

    I have realized that there is a problem with the beautifier of SVEditor in
    the contraint blocks of systemverilog.
    I am using Mars.2 with SVEditor 1.8.3

    Here the snip to reproduce the wrong formatting

    class A ; //base input transaction

    //LEGAL CONSTRAINTconstraint legal_values {
    foreach(A[j]) {
    if ((A!=0)||(B!=7)||(C!=0)) {
    A[j] inside {[16'h0F00:16'h0F03]}; } else {
    A[j] >= 16'h0F00; B[j] + D[j] -1 <= 16'hFFFF;
    }

    //Constraint logical start_address
    A[j] >= 32'h0001_0000;B[j] <= 32'h0002_FFFF;
    

    foreach(A[i]) {
    if ((i!=j)) {
    A[i] > A[j]+B[j]+3; //give 3 bytes separation
    C[i] < C[j]-3;
    }
    } //end foreach Ii
    A[j] inside {[1:$]}
    B[j] inside {[0:7]}; C[j] inside {[0:7]};
    } //loop
    } //end legal values

    endclass :

    Please notice that i have modified the constraints and probably they are
    not compilable. What i wanted to show is that they are not formated
    correctly by the tool.
    Do you know the reason?


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    Related

    Bugs: #418

  • StevenAZ

    StevenAZ - 2016-03-21

    Fixed in 1.8.4

     
  • StevenAZ

    StevenAZ - 2016-03-21
    • status: open --> closed
     

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