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##################################################################
# This AWK script implements GXF parsing
#
#Copyright 2008 Pjotr Kourzanov
#
#This file is part of LIME.
#
#LIME is free software: you can redistribute it and/or modify
#it under the terms of the GNU General Public License version 2
#as published by the Free Software Foundation.
#
#LIME is distributed in the hope that it will be useful,
#but WITHOUT ANY WARRANTY; without even the implied warranty of
#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#GNU General Public License for more details.
#
#You should have received a copy of the GNU General Public License
#along with LIME. If not, see <http://www.gnu.org/licenses/>.
##################################################################
BEGIN {
if (!root) root="@gxf"
if (root=="@") root=""
}
func handle_gxf(tag,body, n,p,i,par,fn,fp,tn,tp,ed,j)
{
if (DEBUG) print "GXF: handling",tag,"in",state >STDERR
# element id
if (tag=="id" && (state ~ /@node$/ ||
state ~ /@port$/ ||
state ~ /@edge$/ ||
state ~ /@sched$/))
return id[lev]=body
if (tag=="type" && (state ~ /@node$/ ||
state ~ /@port$/ ||
state ~ /@edge$/))
return type[lev]=body
if (tag=="ret" && state ~ /@node$/)
return ret[lev]=body
if (tag=="size" && state ~ /@port$/)
return size[lev]=append(size[lev],body,SUBSEP)
if (tag=="const" && state ~ /@port$/)
return const[lev]=1
if (tag=="volatile" && state ~ /@port$/)
return volatile[lev]=1
if (tag=="constp" && state ~ /@port$/)
return constp[lev]=1
if (tag=="volatilep" && state ~ /@port$/)
return volatilep[lev]=1
if (tag=="static" && state ~ /@port$/)
return static[lev]=1
if (tag=="restrict" && state ~ /@port$/)
return restrict[lev]=1
if (tag=="port" && state ~ /@node$/ && state !~ /@edge/)
{
if (Tag[lev] != "node") fail("port not in node")
par=id[lev-1] ? id[lev-1] : f
n=id[lev]
p=id[lev+1]
port_type[par,n,p]=type[lev+1]
port_size[par,n,p]=size[lev+1]
port_const[par,n,p]=const[lev+1]
port_volatile[par,n,p]=volatile[lev+1]
port_constp[par,n,p]=constp[lev+1]
port_volatilep[par,n,p]=volatilep[lev+1]
port_static[par,n,p]=static[lev+1]
port_restrict[par,n,p]=restrict[lev+1]
data_modi[par,n,p]=append(const[lev+1] ? "const" : "", volatile[lev+1] ? "volatile" : "")
port_modi[par,n,p]=append(append(append(append(constp[lev+1] ? "constp" : ""),
volatilep[lev+1] ? "volatilep" : ""),
static[lev+1] ? "static" : ""),
restrict[lev+1] ? "restrict" : "")
ports[par,n,++nports[par,n]]=p
if (const[lev+1])
inports[par,n,port_idx[par,n,p]=++ninports[par,n]]=p
else
outports[par,n,port_idx[par,n,p]=++noutports[par,n]]=p
delete size; delete const; delete static; delete restrict
delete constp; delete volatile; delete volatilep
return body
}
# if (tag=="port" && state ~ /@rule$/) {
# n=id[lev-1]
# p=id[lev+1]
# arule[f,n,arule_idx[f,n,p]=++narule[f,n]]=p
# return body
# }
#
# if (tag=="rule" && state ~ /@node$/) {
# return body
# }
# top-level node or a sub-node
if (tag=="node" && (state==root || state ~ /@node$/))
{
if (state==root) par=f
if (state ~ /@node$/) par=id[lev]
n=id[lev+1]
nodes[par,node_idx[par,n]=++nnodes[par]]=n
node_ret[par,n]=ret[lev+1]
node_type[par,n]=type[lev+1]
if (!nports[par,n]) nports[par,n]=0
if (!ninports[par,n]) ninports[par,n]=0
if (!noutports[par,n]) noutports[par,n]=0
delete ret
return body
}
if (tag=="port" && state ~ /@edge@.*@node$/)
return port[lev]=id[lev+1]
if (tag=="node" && (state ~ /@from$/ ||
state ~ /@to$/))
{
port[lev]=port[lev+1]
return node[lev]=id[lev+1]
}
if (tag=="from" && state ~ /@edge$/) {
from_node[lev]=node[lev+1]
from_port[lev]=port[lev+1]
return body
}
if (tag=="to" && state ~ /@edge$/) {
to_node[lev]=node[lev+1]
to_port[lev]=port[lev+1]
return body
}
if (tag=="edge" && (state==root || state ~ /@node$/)) {
if (state==root) par=f
if (state ~ /@node$/) par=id[lev]
edge_type[par,ed=++nedges[par]]=type[lev+1]
# TODO remove this later
id_edge[edge_id[ed]=id[lev+1]]=ed
fn=from_node[lev+1]; fp=from_port[lev+1]
tn=to_node[lev+1]; tp=to_port[lev+1]
if (port_const[par,fn,fp] || !port_const[par,tn,tp])
fail("mismatch in edge connector types " fn ":" fp "(" port_const[par,fn,fp] ")->("\
port_const[par,tn,tp] ")" tn ":" tp "\nCHECK YOUR GRAPHS AND MODULES")
#print par,fn,fp,"->",tn,tp >STDERR
reg_peer(fn,fp,tn,tp,ed,"write",par)
reg_peer(tn,tp,fn,fp,ed,"read",par)
edge_from[par,ed]=fn SUBSEP fp
edge_to[par,ed]=tn SUBSEP tp
node_out[par,fn,out_idx[par,fn,ed]=++fanout[par,fn]]=ed
node_in[par,tn,in_idx[par,tn,ed]=++fanin[par,tn]]=ed
delete node; delete port
delete from_node; delete from_port
delete to_node; delete to_port
return body
}
if (tag=="node" && state ~ /@sched$/) {
s=id[lev]
order[f,s,++norder[f,s]]=id[lev+1]
return body
}
if (tag=="sched" && state==root) {
comps[f,++ncomps[f]]=id[lev+1]
return body
}
if (relax) {
if (DEBUG) print "GXF: ignoring",tag,"in",state >STDERR
return body
}
fail("GXF: unknown tag " tag)
}
func eval(e) {
return e
}
func Eval(e, cmd,res) {
if (e) {
cmd = "bc"
print e |& cmd
cmd |& getline res
close(cmd)
}
return res
}
func selfport(dir,p,pp) {
if (dir=="write") return p pp
return pp p
}
func reg_peer(n,p,pn,pp,ed,dir,par, pt,ppt,i) {
pt=port_type[par,n,p]
if (!pt) fail("no such port " n ":" p "\nCHECK YOUR GRAPHS AND MODULES")
ppt=port_type[par,pn,pp]
if (!ppt) fail("no such port " pn ":" pp "\nCHECK YOUR GRAPHS AND MODULES")
# TODO: allow only exact matches for now
if (pt!=ppt) {
if (typesizes[pt]==typesizes[ppt]) {
if (!port_static[par,n,p] && !port_static[par,pn,pp])
warn("mismatch in port types " n ":" p "->" pn ":" pp " " pt "!=" ppt)
} else
fail("mismatch in port types " n ":" p "->" pn ":" pp " " pt "!=" ppt "\n"\
"CHECK YOUR GRAPHS AND MODULES")
}
# dimension has to match
if (portdim(par,n,p) != portdim(par,pn,pp))
fail("mismatch in port dimension " n ":" p "->" pn ":" pp " "\
portdim(par,n,p) "!=" portdim(par,pn,pp) "\n"\
"CHECK YOUR GRAPHS AND MODULES")
# all dimension sizes have to match except the first one
for (i=2; i<portdim(par,n,p); i++)
if (portsize(par,n,p,i)!=portsize(par,pn,pp,i))
fail("mismatch in dimension size " n ":" p "->" pn ":" pp " "\
portsize(par,n,p,i) "!=" portsize(par,pn,pp,i) "\n"\
"CHECK YOUR GRAPHS AND MODULES")
# constructor edges
if (edge_type[par,ed] ~ /^init/) {
init_node[par,n,p]=pn
init_port[par,n,p]=pp
init_edge[par,n,p]=ed
init_dir[par,n,p]=dir
if (dir == "write") {
cons[par,n,cons_idx[par,n,p]=++ncons[par,n]]=p
if ((par,n) in constructors_idx); else
constructors[par,constructors_idx[par,n]=++nconstructors[par]]=n
}
} else if (edge_type[par,ed] ~ /^deinit/) {
# destructor edges
deinit_node[par,n,p]=pn
deinit_port[par,n,p]=pp
deinit_edge[par,n,p]=ed
deinit_dir[par,n,p]=dir
if (dir == "read") {
dstr[par,n,dstr_idx[par,n,p]=++ndstr[par,n]]=p
if ((par,n) in destructors_idx); else
destructors[par,destructors_idx[par,n]=++ndestructors[par]]=n
}
} else {
if (((par,n,p) in peer_node) && pn!=peer_node[par,n,p])
fail("node endpoint can not be bound twice: "\
par ":" n ":" p " (" peer_node[par,n,p] ")!=(" pn ")")
peer_node[par,n,p]=pn
if (((par,n,p) in peer_port) && pp!=peer_port[par,n,p])
fail("port endpoint can not be bound twice: "\
par ":" n ":" p " (" peer_port[par,n,p] ")!=(" pp ")")
peer_port[par,n,p]=pp
if (((par,n,p) in peer_edge) && ed!=peer_edge[par,n,p])
fail("endpoint can not be bound twice: "\
par ":" n ":" p " (" peer_edge[par,n,p] ")!=(" ed ")")
peer_edge[par,n,p]=ed
if (((par,n,p) in peer_dir) && dir!=peer_dir[par,n,p])
fail("endpoint sex can not be bound twice: "\
par ":" n ":" p " (" peer_dir[par,n,p] ")!=(" dir ")")
peer_dir[par,n,p]=dir
}
# state edges
if (edge_type[par,ed] ~ /state/) {
if ((par,n,p) in stateport_idx); else
stateports[par,n,dir,stateport_idx[par,n,p]=++nstateports[par,n,dir]]=p
# XXX: propagate "statefullness" to the parent
if (par!=f) if ((f,par,p) in stateport_idx); else
stateports[f,par,dir,stateport_idx[f,par,p]=++nstateports[f,par,dir]]=p
# self-edge
if (n==pn) if ((par,n) in stateful_idx); else
statefuls[par,stateful_idx[par,n]=++nstatefuls[par]]=n
# TODO: allow only exact matches for now
if (port_size[par,n,p]!=port_size[par,pn,pp])
if (eval(port_size[par,n,p]) != eval(port_size[par,pn,pp]))
fail("mismatch in port cardinality " n ":" p "->" pn ":" pp " "\
eval(port_size[par,n,p]) "!=" eval(port_size[par,pn,pp]) "\n"\
"STATE PORTS MUST HAVE SAME CARDINALITY")
if (port_restrict[par,n,p] || port_restrict[par,pn,pp])
fail("shmem/state ports can not be restricted!")
}
if (edge_type[par,ed] ~ /fifo/) {
if (edge_type[par,ed] ~ /^init/) {
if ((par,n,p) in delayport_idx); else
delayports[par,n,dir,delayport_idx[par,n,p]=++ndelayports[par,n,dir]]=p
# XXX: propagate "delayedness" to the parent
if (par!=f) if ((f,par,p) in delayport_idx); else
delayports[f,par,dir,delayport_idx[f,par,p]=++ndelayports[f,par,dir]]=p
if (dir=="read") {
if ((par,n) in delayed_idx); else
delayed[par,delayed_idx[par,n]=++ndelayed[par]]=n
}
} else if (edge_type[par,ed] ~ /^deinit/) {
if ((par,n,p) in rushport_idx); else
rushports[par,n,dir,rushport_idx[par,n,p]=++nrushports[par,n,dir]]=p
# XXX: propagate "rushfullness" to the parent
if (par!=f) if ((f,par,p) in rushport_idx); else
rushports[f,par,dir,rushport_idx[f,par,p]=++nrushports[f,par,dir]]=p
if (dir=="write") {
if ((par,n) in rushed_idx); else
rushed[par,rushed_idx[par,n]=++nrushed[par]]=n
}
} else {
# regular fifos
if ((par,n,p) in fifo_idx); else
fifos[par,n,dir,fifo_idx[par,n,p]=++nfifos[par,n,dir]]=p
if (par!=f) if ((f,par,p) in fifo_idx); else
fifos[f,par,dir,fifo_idx[f,par,p]=++nfifos[f,par,dir]]=p
if ((par,n) in actors_idx); else
actors[par,actors_idx[par,n]=++nactors[par]]=n
}
}
}
func portdim(f,n,p, ps) { return split(port_size[f,n,p],ps,SUBSEP) }
func get_portdecl(f,n,p) { return suff(data_modi[f,n,p]," ")\
port_type[f,n,p] " " p get_aportsizes(f,n,p) }
func get_aportsizes(f,n,p, nd,ps,i,r) {
nd=split(port_size[f,n,p],ps,SUBSEP)
# XXX: hack for ARM/EVP dumbass compilers
if (eval(ps[1])==0) ps[1]="ZERO"
r=r "[" (do_modi ? suff(port_modi[f,n,p]," ") : "") ps[1] "]"
for (i=2; i<=nd; i++) {
# XXX: hack for ARM/EVP dumbass compilers
if (eval(ps[i])==0) ps[i]="ZERO"
r=r "[" ps[i] "]"
}
return r
}
func get_portdef(f,n,p) { return port_type[f,n,p] " " p get_portsizes(f,n,p) }
func get_portsizes(f,n,p, nd,ps,i,r) {
nd=split(port_size[f,n,p],ps,SUBSEP)
for (i=1; i<=nd; i++) {
# XXX: hack for ARM/EVP dumbass compilers
if (eval(ps[i])==0) ps[i]="ZERO"
r=r "[" ps[i] "]"
}
return r
}
func xml_portsizes(f,n,p,l, nd,ps,i) {
nd=split(port_size[f,n,p],ps,SUBSEP)
for (i=1; i<=nd; i++)
print space(l) "<size>" ps[i] "</size>"
}
func portsize(f,n,p,d, nd,ps,i,r) {
nd=split(port_size[f,n,p],ps,SUBSEP)
if (d>nd) fail("no such dimension")
if (d<=nd && d>0) return ps[d]
for (i=1; i<=nd; i++)
r=append(r,ps[i],"*")
return r
}
@include xml-parser.awk

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