STM8S001J3 working

[Jaromir Sukuba]

Hello,
I tested new 8-pin STM8S001J3 devices with STM8 GDB project. Since those devices lack NRST pin, I had to create stm8nr.cfg file

# script for stm8 family

#
# stm8 devices support SWIM transports only.
#

transport select stlink_swim

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm8
}

# Work-area is a space in RAM used for flash programming
# By default use 1kB
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x400
}

if { [info exists FLASHSTART] } {
   set _FLASHSTART $FLASHSTART
} else {
   set _FLASHSTART 0x8000
}

if { [info exists FLASHEND] } {
   set _FLASHEND $FLASHEND
} else {
   set _FLASHEND 0xffff
}

if { [info exists EEPROMSTART] } {
   set _EEPROMSTART $EEPROMSTART
} else {
   set _EEPROMSTART 0x4000
}

if { [info exists EEPROMEND] } {
   set _EEPROMEND $EEPROMEND
} else {
   set _EEPROMEND 0x43ff
}

if { [info exists OPTIONSTART] } {
   set _OPTIONSTART $OPTIONSTART
} else {
   set _OPTIONSTART 0x4800
}

if { [info exists OPTIONEND] } {
   set _OPTIONEND $OPTIONEND
} else {
   set _OPTIONEND 0x487f
}

if { [info exists BLOCKSIZE] } {
   set _BLOCKSIZE $BLOCKSIZE
} else {
   set _BLOCKSIZE 0x80
}

hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0

set _TARGETNAME $_CHIPNAME.cpu

target create $_TARGETNAME stm8 -chain-position stm8.cpu

$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE

if { [info exists ENABLE_STEP_IRQ] } {
   $_TARGETNAME configure -enable_step_irq
}

if { [info exists ENABLE_STM8L] } {
   $_TARGETNAME configure -enable_stm8l
}

adapter_khz 0

# reset_config srst_only

#uncomment this line to connect under reset
#reset_config srst_nogate connect_assert_srst

notice the "# reset_config srst_only" line - I disabled RESET handling. Then I created stm8s001.cfg file, being direct top-level entry for openocd, utilizing the newly created stm8nr.cfg:

#config script for STM8S001

#set ENABLE_STEP_IRQ 1
set FLASHEND 0x9FFF
set BLOCKSIZE 0x40

proc stm8_reset_rop {} {
   mwb 0x4800 0x00
   reset halt
}

source [find target/stm8nr.cfg]

And everything works as expected.

Side note:
The STM8S001J3 can get OTP easily, just stop bering careful when configuring IO pins, citation from datasheet.

As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever. This initial delay can be removed in the final (locked) code.

As SWIM pin is shared with PD1, PD3, PD5 abd PC6 pins (this is apparently chip intended for larger package, looks like chip for STM8S0003), chances of screwing up the GPIO configuration are somewhat higher.

[Jaromir Sukuba]

Now I created new config file for STM8S001J3, not needing stm8nr.cfg file anymore

# script for stm8 family

#
# stm8 devices support SWIM transports only.
#

proc stm8_reset_rop {} {
   mwb 0x4800 0x00
   reset halt
}

transport select stlink_swim

  set _CHIPNAME stm8

# Work-area is a space in RAM used for flash programming
# By default use 1kB
   set _WORKAREASIZE 0x400
   set _FLASHSTART 0x8000
   set _FLASHEND 0x9FFF
   set _EEPROMSTART 0x4000
   set _EEPROMEND 0x43ff
   set _OPTIONSTART 0x4800
   set _OPTIONEND 0x487f
   set _BLOCKSIZE 0x40

hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME stm8 -chain-position stm8.cpu

$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
   $_TARGETNAME configure -enable_step_irq

adapter_khz 0

# reset_config srst_only

#uncomment this line to connect under reset
#reset_config srst_nogate connect_assert_srst

It doesn't utilize universal stm8.cfg, it has everything in single file.

[akre]

Thanks for your good work,

what about just call the stm8.cfg then on the next line add "reset_config none" ?

#config script for STM8S001

#set ENABLE_STEP_IRQ 1
set FLASHEND 0x9FFF
set BLOCKSIZE 0x40

proc stm8_reset_rop {} {
   mwb 0x4800 0x00
   reset halt
}

source [find target/stm8.cfg]

reset_config none

[Jaromir Sukuba]

I wasn't aware I can "reconfigure" the reset config so easily. I tested your setup, works as well and unlike my two attempts, it's simple and elegant, thanks.