It looks like I'm having some trouble using my STM8L Discovery board with OpenOCD. Note that I am using the onboard ST-Link that is built into the development board.
Environment is running in Cygwin64.
Issue #1: Problems with reset
Starting up with "reset halt" fails:
$ openocd -f interface/stlink-v2.cfg -f target/stm8l152.cfg -c "init" -c "reset halt"
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: RCLK - adaptive
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 0 kHz, using 5 kHz
Info : Unable to match requested speed 0 kHz, using 5 kHz
Info : RCLK (adaptive clock speed) not supported - fallback to 5 kHz
Info : STLINK v2 JTAG v0 API v1 SWIM v6 VID 0x0483 PID 0x3748
Info : using stlink api v1
TARGET: stm8.cpu - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'
However, I can make a connection if I omit "reset halt":
$ openocd -f interface/stlink-v2.cfg -f target/stm8l152.cfg -c "init"
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: RCLK - adaptive
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 0 kHz, using 5 kHz
Info : Unable to match requested speed 0 kHz, using 5 kHz
Info : RCLK (adaptive clock speed) not supported - fallback to 5 kHz
Info : STLINK v2 JTAG v0 API v1 SWIM v6 VID 0x0483 PID 0x3748
Info : using stlink api v1
Upon connecting via telnet, this is the result of attempting a "reset" and a "reset halt":
$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* stm8.cpu stm8 big stm8.cpu halted
> reset
Polling target stm8.cpu failed, trying to reexamine
trying to reconnect
target halted due to undefined, pc: 0x00006000
> reset halt
TARGET: stm8.cpu - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'
Polling target stm8.cpu failed, trying to reexamine
trying to reconnect
target halted due to debug-request, pc: 0x00006000
>
It looks like the board is physically resetting every time reset is called, so that part is working at least.
Issue 2: Problems with flash
All flash commands fail:
>
>
> flash info 0
invalid subcommand "info 0"
in procedure 'flash'
> flash probe
invalid subcommand "probe"
in procedure 'flash'
> flash
flash
flash bank bank_id driver_name base_address size_bytes chip_width_bytes
bus_width_bytes target [driver_options ...]
flash banks
flash init
flash list
gdb_flash_program ('enable'|'disable')
mflash
mflash bank soc_type base_addr pin_id target
mflash init
nand
program <filename> [address] [verify] [reset] [exit]
stm8 enable_stm8l [1/0]
stm8.cpu stm8 enable_stm8l [1/0]
flash : command requires more arguments
in procedure 'flash'
> program blinky.ihx
TARGET: stm8.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 500
in procedure 'ocd_bouncer'
embedded:startup.tcl:476: Error: ** Unable to reset target **
in procedure 'program'
in procedure 'program_error' called at file "embedded:startup.tcl", line 501
at file "embedded:startup.tcl", line 476
Polling target stm8.cpu failed, trying to reexamine
trying to reconnect
target halted due to debug-request, pc: 0x00006000
Any suggestions?
Last edit: Logan 2017-08-17
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Hello and thanks for your interest in the stm8 binutils project.
For the first issue I just ran the same command line on my stm8l152 discovery board with built in stlink without problems. I would need a debug log (i.e. use -d3 flag on command line) to be able to do further analysis. I do how ever know if you already have some code on the chip running it could prevent proper swim entry. Try change your stm8.cfg file and remove the last comment to enable "connect under reset" : reset_config srst_nogate connect_assert_srst
For the second issue, the stm8 openocd target driver does not have the regular "flash" commands. Just download or flash with openocd command "load_image" or with gdb command "load"
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Just let me know if there is anything else I can provide that might help.
As far as the flashing issue, I was able to follow your advice and use the load_image command to successfully flash a file. It might be good to add an example of this to the main page so others don't make the same mistakes!
Thank you for all the work you put into this project. It's been extremely helpful in getting my STM8 development environment up and running!
Last edit: Logan 2017-08-18
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
New openocd with improved reset handling (cygwin64).
The problem is after reset was deasserted it takes some time before cpu comes out of reset. So I added a call to target_poll immediatley after deassert. This will keep openocd call stm8_poll until it is halted or it times out.
Test and report any issues. If it works will add this patch to the source package.
Swapped in the patched version of openocd.exe. Looks like it's working as it should:
$ openocd -f interface/stlink-v2.cfg -f target/stm8l152.cfg -c "init" -c "reset halt"
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: RCLK - adaptive
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 0 kHz, using 5 kHz
Info : Unable to match requested speed 0 kHz, using 5 kHz
Info : RCLK (adaptive clock speed) not supported - fallback to 5 kHz
Info : STLINK v2 JTAG v0 API v1 SWIM v6 VID 0x0483 PID 0x3748
Info : using stlink api v1
target halted due to debug-request, pc: 0x00006000
It looks like I'm having some trouble using my STM8L Discovery board with OpenOCD. Note that I am using the onboard ST-Link that is built into the development board.
Environment is running in Cygwin64.
Issue #1: Problems with reset
Starting up with "reset halt" fails:
However, I can make a connection if I omit "reset halt":
Upon connecting via telnet, this is the result of attempting a "reset" and a "reset halt":
It looks like the board is physically resetting every time reset is called, so that part is working at least.
Issue 2: Problems with flash
All flash commands fail:
> > > flash info 0 invalid subcommand "info 0" in procedure 'flash' > flash probe invalid subcommand "probe" in procedure 'flash' > flash flash flash bank bank_id driver_name base_address size_bytes chip_width_bytes bus_width_bytes target [driver_options ...] flash banks flash init flash list gdb_flash_program ('enable'|'disable') mflash mflash bank soc_type base_addr pin_id target mflash init nand program <filename> [address] [verify] [reset] [exit] stm8 enable_stm8l [1/0] stm8.cpu stm8 enable_stm8l [1/0] flash : command requires more arguments in procedure 'flash' > program blinky.ihx TARGET: stm8.cpu - Not halted in procedure 'program' in procedure 'reset' called at file "embedded:startup.tcl", line 500 in procedure 'ocd_bouncer' embedded:startup.tcl:476: Error: ** Unable to reset target ** in procedure 'program' in procedure 'program_error' called at file "embedded:startup.tcl", line 501 at file "embedded:startup.tcl", line 476 Polling target stm8.cpu failed, trying to reexamine trying to reconnect target halted due to debug-request, pc: 0x00006000Any suggestions?
Last edit: Logan 2017-08-17
Hello and thanks for your interest in the stm8 binutils project.
For the first issue I just ran the same command line on my stm8l152 discovery board with built in stlink without problems. I would need a debug log (i.e. use -d3 flag on command line) to be able to do further analysis. I do how ever know if you already have some code on the chip running it could prevent proper swim entry. Try change your stm8.cfg file and remove the last comment to enable "connect under reset" : reset_config srst_nogate connect_assert_srst
For the second issue, the stm8 openocd target driver does not have the regular "flash" commands. Just download or flash with openocd command "load_image" or with gdb command "load"
I meant of course uncomment the last line in stm8.cfg to enable connect under reset.
Result of running command again with -d3 flag added:
Same thing, but with the last line of stm8.cfg uncommented:
Just let me know if there is anything else I can provide that might help.
As far as the flashing issue, I was able to follow your advice and use the load_image command to successfully flash a file. It might be good to add an example of this to the main page so others don't make the same mistakes!
Thank you for all the work you put into this project. It's been extremely helpful in getting my STM8 development environment up and running!
Last edit: Logan 2017-08-18
Seems something is going wrong during startup. Perhaps some kind of race condition....
Just for the sake of it, could you run cygcheck -c openocd
Result of cygcheck -c openocd:
$ cygcheck -c openocd Cygwin Package Information Package Version Status openocd 0.10.0-20170525 OKTry this version with -d3, it has some extra debug logs enabled.
If you run this from a temporary directory you will have to add search path to the scripts dir.
$ ./openocd -s /usr/local/share/openocd/scripts -d3 -f interface/stlink-v2.cfg -f target/stm8l152.cfg -c "init" -c "reset halt" 2>&1 | tee /cygdrive/c/temp/openocd.log
Results below. Seems to get stuck while polling -- had to end the process with Ctrl-C.
Yea, it is normal, stm8_poll is called every few 100ms. That's why those msg are disabled not to spam the debug log...
How ever, did you notice it does not show "TARGET: stm8.cpu - Not halted" anymore?
Infact, I did make a small change to the code with regard to the target state. The target state variable was not updated to "halted" after reset...
It could of course still be a race condition issue but I could make you a release version to see if the problem is gone...
Ah -- that makes sense. Sorry for any dumb questions/statements, I'm still getting up to speed on OpenOCD.
I would be happy to test out a release version if you can put one together for me.
New openocd with improved reset handling (cygwin64).
The problem is after reset was deasserted it takes some time before cpu comes out of reset. So I added a call to target_poll immediatley after deassert. This will keep openocd call stm8_poll until it is halted or it times out.
Test and report any issues. If it works will add this patch to the source package.
And the patch for those who are interested.
Swapped in the patched version of openocd.exe. Looks like it's working as it should:
Again, with debug mode enabled:
Thank you for resolving this so quickly!