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Posted by
2019-05-26
New interrupt model
Steem 4.0 will feature a new interrupt model.
The real MC68000 checks for interrutps sometime during the instruction, not between instructions as in the previous model (Motorola Application Note 1012). More precisely, it scans the IPL (Interrupt Priority Level) pins every cycle, but it makes the decision to take an interrupt at a point defined by microcodes, once per instruction (Motorola patent US4325121, ijor's FX68K FPGA core).
The new model is based on this. We don't check IPL every cycle, but we emulate the last TVN (trap vector number) latch. Generally, it happens when the second operand of the prefetch queue is being fetched, but there are a few exceptions, notably the one described in AN1012 (MOVEM).
For the record, I first used the patent to place the macros, later checked with FX68K and there were only a few corrections!
It is a significant change in CPU emulation, that naturally brings on other changes. Some timings are shifted (MFP, HBL, VBL...).
Even the "emulator cycle" reference, based on the HBL interrupt, is affected!
Because everything was tuned together, few programs are visibly improved by this. Maybe the terrible Phantom scroller, 3615GEN4-HMD...
Phantom
Hi Steven !
Great work, as usual. But please note that interrupt timing doesn't depend so much on TVN latch time. The timing actually depends on when interrupt pending is latched. See the "rInterrupt" register and the grp1LatchEn variable in my FPGA code. TVN latch just checks this register.
Cheers and keep up the good work!
Ijor
Thx ijor, the same for you.
Actually dbi in the patent and that grp1LatchEn variable in FX68K were used to place the "check IPL" timing in each instruction, so you're right, the text could be more precise. By last TVN latch I meant last latch of rInterrupt that would change TVN, maybe that would be more correct.
Ah, ok. Yeah, the text is a bit misleading.
Cheers,