Re: [Squeak-VMdev] Versiojn 4 changes

[Tim R. <ti...@su...>]

In message <6FE...@in...>
          Ian Piumarta <ian...@in...> wrote:


> 
> Current version:
> 
>          lwz     r3,0xfffc(r27)
>          lwz     r4,0(r27)
>          and     r28,r3,r4
>          andi.   r9,r28,0x1
>          beq     <fail>
>          srawi   r5,r3,1
>          srawi   r0,r4,1
>          add     r4,r5,r0
>          rlwinm  r2,r4,1,0,30
>          xor.    r9,r4,r2
>          blt     <fail>
>          ori     r6,r2,0x1
>          stwu    r6,0xfffc(r27)
>          <dispatch>
>
Just out of interest I extracted the RISC OS equivalent and I'm pleased
to see that the latest compiler does a reasonable job. Probably why it
makes a VM 20% faster than the old one...

	LDR	R0,[R5] 		get rcvr & arg from stack
	LDR	R2,[R5,#-4]
	AND	R1,R2,R0                do tag test
	TST	R1,#1
	BEQ	fail smallint test
	MOV	R1,R2,ASR #1            shift dn arg
	ADD	R0,R1,R0,ASR #1         add shifted arg to shifted rcvr
	EORS	R1,R0,R0,LSL #1         eor result with itself shifted up
	BMI	fail result test
	MOV	R1, #1                  odd- put 1 in R0?
	ORR	R1,R0,R0,LSL #1         or in 1 to result shifted up
	STR	R0,[R5,#-4]!            push & modify sp in one go
	LDRB	R7,[R6,R1]!             fetch next byte - odd use R0 for 1
	B	dispatch

It's hard to see much that could be dropped (in the context of an
interpreter). If we could keep the top couple of items in registers it
would save two loads and a store. Even a translator would have to do
most of this I think; no load or store or bytecode fetch I guess? 


tim
--
Tim Rowledge, ti...@su..., http://sumeru.stanford.edu/tim
People who deal with bits should expect to get bitten.  - Jon Bentley