spadger / Blog: Recent posts

Spadger is a small animal that can fly, which can be borrowed here to describe the MIPS verilog implementation with sub-instructions. Hope it will be extended to complex MIPS architecture by myself. The roadmap of the spadger is
1. MipsCpu0.1-Multicycle MIPS Verilog Implementation, un-verified.
2. MipsCpu0.2-Pipelined MIPS Verilog Implementation, un-verified.
3. MipsCpu0.3-Deep Pipelined MIPS Verilog Implementation, verified.
4. MipsCpu0.4-Sysnthesized version.
5. MipsCpu0.5-FPGA verified version.
6. MipsCpu0.6-64bit Deep Pipelined Implementation.