Recent changes to DSHardware

DSHardware modified by Wiesner Thomas

Wiesner Thomas — Sun, 03 Nov 2013 10:15:30 -0000

--- v1
+++ v2
@@ -15,9 +15,9 @@

 #### Support circuitry ####

-Lets start with the power supply section in the lower left corner. There's not much to dwell about; Just a standard linear voltage regulator circuit with protection diodes. The 5V output voltage simultaneously serves as supply voltage and reference voltage. Note that the comparator and opamp are supplied directly by the battery voltage. The voltage regulator needs at least around 1.5V more input voltage than output voltage (the amount depends on the exact type, but unless you use a low-drop regulator, you won't be able to get much less dropout voltage). On the other hand, the input common mode range of the opamp/comparator goes from 0V to Vcc-1.5V and the output voltage range is even lower. Thus, by using e.g. 9V supply voltage and connecting the opamp and comparator supply directly to the battery we buy enough headroom to flawlessly work in the voltage range from 0V to 5V.
+Lets start with the power supply section in the lower left corner. There's not much to dwell about; Just a standard linear voltage regulator circuit with protection diodes. The 5V output voltage simultaneously serves as supply voltage and reference voltage. Note that the comparator and opamp are supplied directly by the battery voltage. The voltage regulator needs at least around 1.5V more input voltage than output voltage (the amount depends on the exact type, but unless you use a low-drop regulator, you won't be able to get much less dropout voltage). On the other hand, the input common mode range of the opamp/comparator goes from 0V to *Vcc*-1.5V and the output voltage range is even lower. Thus, by using e.g. 9V supply voltage and connecting the opamp and comparator supply directly to the battery we buy enough headroom to flawlessly work in the voltage range from 0V to 5V.

-The clock generator is in the center and built around the well known Schmitt-Trigger opamp or comparator square wave generator schematic. *R101*, *R102* and *R103* together with *U2A* form an inverting Schmitt-Trigger. The three equal resistors set the thresholds to 1/3\*Vref and 2/3\*Vref. The input of the Schmitt-Trigger (the (-) input of the comparator) is connected the RC-network *R100*/*C100*. If *C100*'s voltage drops below 1/3\*Vref, the output of the comparator will go high (approximately Vref) and start to charge *C100*. Once the capacitor voltage reaches 2/3\*Vref, the comparator output will switch back to low and discharge *C100* again and the process repeats. Fortunately, no special long term stability is required for the DSADC to work correctly, so this simple RC clock generator is sufficient.
+The clock generator is in the center and built around the well known Schmitt-Trigger opamp or comparator square wave generator schematic. *R101*, *R102* and *R103* together with *U2A* form an inverting Schmitt-Trigger. The three equal resistors set the thresholds to 1/3\**Vref* and 2/3\**Vref*. The input of the Schmitt-Trigger (the (-) input of the comparator) is connected the RC-network *R100*/*C100*. If *C100*'s voltage drops below 1/3\**Vref*, the output of the comparator will go high (approximately *Vref*) and start to charge *C100*. Once the capacitor voltage reaches 2/3\**Vref*, the comparator output will switch back to low and discharge *C100* again and the process repeats. Fortunately, no special long term stability is required for the DSADC to work correctly, so this simple RC clock generator is sufficient.
 *U3B* is used to divide the clock frequency by a factor of two. The output of *U3B* has a perfect 50% duty cycle and clean logic level. There's actually no reason to be that picky about the duty cycle but the 7474 contains two D-FFs and the second one is leftover anyway.

 #### Delta sigma converter ####
@@ -26,19 +26,19 @@
 While no special long term stability of the integration capacitor *C201* is required, I recommend to use some decent foil capacitor. Avoid any type of electrolytic capacitors because of leakage and general purpose supply ("blocking capacitors") because of their potential nonlinearity.

 I won't give an in-depth explanation how a DSADC works, because you can look it up somewhere else, but some general overview.
-I didn't want to use a dual supply (positive and negative supply voltage). Therefore, the reference voltage is split in half by *R1*/*R2* and the AC impedance of this 2.5V reference potential is lowered somewhat by *C1*. These 2.5V (= Vref/2) serve as virtual ground. *R204* in the SDADC shifts the input voltage range in such a way that a symmetric input (with respect to the "real" ground) is achieved, despite the 2.5V virtual ground.
+I didn't want to use a dual supply (positive and negative supply voltage). Therefore, the reference voltage is split in half by *R1*/*R2* and the AC impedance of this 2.5V reference potential is lowered somewhat by *C1*. These 2.5V (= *Vref*/2) serve as virtual ground. *R204* in the SDADC shifts the input voltage range in such a way that a symmetric input (with respect to the "real" ground) is achieved, despite the 2.5V virtual ground.

 *U2B* serves as a 1-bit analog to digital converter. It just tells us whether the output of the integrator is above of below virtual ground. The D-FF *U3A* is used as a clocked 1-bit digital to analog converter. It outputs either -2.5V or 2.5V with respect to the virtual ground. Note that *U3A* must be a type with CMOS output state (e.g. a HCMOS type), because bipolar logic ICs (e.g. LS series) don't provide clean 0V and 5V logic output levels which is very inportant in this application.

 So, how does the analog to digital conversion work? One way to look at it is the following: Consider the input (pin 6) of the integrator *U1B*. It is a current summing node (leave out *R204* for now as it just shifts the input range). The current sum at this node is what the integrator integrates. While doing so, *U1B* keeps the input (pin 6) at (virtual) ground.
 We therefore compare the current caused by the input voltage (which flows through *R201*) to the current fed back from the output of the D-FF, flowing through *R202*.
-Assume that the input voltage is virtual ground (2.5V). This would cause no current to flow through *R201*, because the summing node pin 6 is held at virtual ground by *U1B* and thus the voltage across *R201* is zero. The output of the D-FF is either Vref/2 above virtual ground (5V = Vref) or Vref/2 below virtual ground (0V).
+Assume that the input voltage is virtual ground (2.5V). This would cause no current to flow through *R201*, because the summing node pin 6 is held at virtual ground by *U1B* and thus the voltage across *R201* is zero. The output of the D-FF is either *Vref*/2 above virtual ground (5V = *Vref*) or *Vref*/2 below virtual ground (0V).

-If you now assume that we started with an initial output voltage of Vref/2, we would integrate alternatingly up and down the same amounts each clock cycle because the comparator trips at Vref/2. The integrator slope is determined by the current sum at the input node. In this case, as there is no current through *R201*, the rising and falling slopes are equal. The output of the D-FF would be the bitstream 01010101... . If you take now the average of the bitstream you get exactly 0.5, meaning the input voltage is 0.5 times the reference voltage (5V) which is 2.5V in our case, just the assumption we started with!
+If you now assume that we started with an initial output voltage of *Vref*/2, we would integrate alternatingly up and down the same amounts each clock cycle because the comparator trips at *Vref*/2. The integrator slope is determined by the current sum at the input node. In this case, as there is no current through *R201*, the rising and falling slopes are equal. The output of the D-FF would be the bitstream 01010101... . If you take now the average of the bitstream you get exactly 0.5, meaning the input voltage is 0.5 times the reference voltage (5V) which is 2.5V in our case, just the assumption we started with!

-How does all this change, if the input voltage is not at virtual ground? To investigate this, assume Vin > 2.5V. In this case, we integrate faster down than up (keep in mind that the integrator is inverting). In this case, the output won't alternate each clock cycle, because we need more shallower up-integrating cycles to compensate the steeper slope of the down-integrating cycles. This in turn means that the output Q of *U3A* is more often low than high and the output /Q os more often high than low. The average of the bitstream is now higher than 0.5, which is totally in accordance with our assumption, Vin > Vref/2.
+How does all this change, if the input voltage is not at virtual ground? To investigate this, assume *Vin* > 2.5V. In this case, we integrate faster down than up (keep in mind that the integrator is inverting). In this case, the output won't alternate each clock cycle, because we need more shallower up-integrating cycles to compensate the steeper slope of the down-integrating cycles. This in turn means that the output Q of *U3A* is more often low than high and the output /Q os more often high than low. The average of the bitstream is now higher than 0.5, which is totally in accordance with our assumption, *Vin* > *Vref*/2.

-To make the long story short, the circuit figures out how many times (or how long) you have to add either -Vref/2 or +Vref/2 to your input voltage to get 0V, on average.
+To make the long story short, the circuit figures out how many times (or how long) you have to add either -*Vref*/2 or +*Vref*/2 to your input voltage to get 0V, on average.

 The given values in the schematic result in an input voltage range of -5V to +5V, of which only -4V to 4V should be used, because the more the input voltage approaches the limits, the less frequently the output bit value changes. In the extreme case (+5V or -5V) you end up with only ones or zeros at the output, but the software which processes the bitstream needs 0-to-1 and 1-to-0 transitions to detect the bit level voltages correctly.

DSHardware modified by Wiesner Thomas

Wiesner Thomas — Sun, 03 Nov 2013 10:12:51 -0000

Delta Sigma analog to digital converter hardware

Warning

The described hardware is intended for connection to a soundcard. Keep in mind that your soundcard (and everything else connected to it, including your PC) may be destroyed if something goes wrong. The developers of this project are not responsible for any damage caused by the described hardware or the instructions.

Schematic

The schematic and the KiCad project are available in the downloads section of the project in the hardware-folder.

Brief description

Before reading this section, you should get the hardware documentation from the source mentioned above to know what we are talking about.

This "second generation" hardware of this project is a fully fledged delta sigma analog to digital converter (DSADC) and seems to be one of very few complete and functioning schematics for a DSADC which can be built from standard linear and logic ICs. (You can try to find another one, but you'll mostly find sketches which explain the principles of an DSADC and information on how to design an DSADC chip but hardly complete schematics of one that you can build yourself.)

Support circuitry

Lets start with the power supply section in the lower left corner. There's not much to dwell about; Just a standard linear voltage regulator circuit with protection diodes. The 5V output voltage simultaneously serves as supply voltage and reference voltage. Note that the comparator and opamp are supplied directly by the battery voltage. The voltage regulator needs at least around 1.5V more input voltage than output voltage (the amount depends on the exact type, but unless you use a low-drop regulator, you won't be able to get much less dropout voltage). On the other hand, the input common mode range of the opamp/comparator goes from 0V to Vcc-1.5V and the output voltage range is even lower. Thus, by using e.g. 9V supply voltage and connecting the opamp and comparator supply directly to the battery we buy enough headroom to flawlessly work in the voltage range from 0V to 5V.

The clock generator is in the center and built around the well known Schmitt-Trigger opamp or comparator square wave generator schematic. R101, R102 and R103 together with U2A form an inverting Schmitt-Trigger. The three equal resistors set the thresholds to 1/3*Vref and 2/3*Vref. The input of the Schmitt-Trigger (the (-) input of the comparator) is connected the RC-network R100/C100. If C100's voltage drops below 1/3*Vref, the output of the comparator will go high (approximately Vref) and start to charge C100. Once the capacitor voltage reaches 2/3*Vref, the comparator output will switch back to low and discharge C100 again and the process repeats. Fortunately, no special long term stability is required for the DSADC to work correctly, so this simple RC clock generator is sufficient.
U3B is used to divide the clock frequency by a factor of two. The output of U3B has a perfect 50% duty cycle and clean logic level. There's actually no reason to be that picky about the duty cycle but the 7474 contains two D-FFs and the second one is leftover anyway.

Delta sigma converter

The delta sigma circuit itself is located in the upper left part of the schematic. It consists of the integrator around U1B, the comparator U2B and the D-FF U3A.
While no special long term stability of the integration capacitor C201 is required, I recommend to use some decent foil capacitor. Avoid any type of electrolytic capacitors because of leakage and general purpose supply ("blocking capacitors") because of their potential nonlinearity.

I won't give an in-depth explanation how a DSADC works, because you can look it up somewhere else, but some general overview.
I didn't want to use a dual supply (positive and negative supply voltage). Therefore, the reference voltage is split in half by R1/R2 and the AC impedance of this 2.5V reference potential is lowered somewhat by C1. These 2.5V (= Vref/2) serve as virtual ground. R204 in the SDADC shifts the input voltage range in such a way that a symmetric input (with respect to the "real" ground) is achieved, despite the 2.5V virtual ground.

U2B serves as a 1-bit analog to digital converter. It just tells us whether the output of the integrator is above of below virtual ground. The D-FF U3A is used as a clocked 1-bit digital to analog converter. It outputs either -2.5V or 2.5V with respect to the virtual ground. Note that U3A must be a type with CMOS output state (e.g. a HCMOS type), because bipolar logic ICs (e.g. LS series) don't provide clean 0V and 5V logic output levels which is very inportant in this application.

So, how does the analog to digital conversion work? One way to look at it is the following: Consider the input (pin 6) of the integrator U1B. It is a current summing node (leave out R204 for now as it just shifts the input range). The current sum at this node is what the integrator integrates. While doing so, U1B keeps the input (pin 6) at (virtual) ground.
We therefore compare the current caused by the input voltage (which flows through R201) to the current fed back from the output of the D-FF, flowing through R202.
Assume that the input voltage is virtual ground (2.5V). This would cause no current to flow through R201, because the summing node pin 6 is held at virtual ground by U1B and thus the voltage across R201 is zero. The output of the D-FF is either Vref/2 above virtual ground (5V = Vref) or Vref/2 below virtual ground (0V).

If you now assume that we started with an initial output voltage of Vref/2, we would integrate alternatingly up and down the same amounts each clock cycle because the comparator trips at Vref/2. The integrator slope is determined by the current sum at the input node. In this case, as there is no current through R201, the rising and falling slopes are equal. The output of the D-FF would be the bitstream 01010101... . If you take now the average of the bitstream you get exactly 0.5, meaning the input voltage is 0.5 times the reference voltage (5V) which is 2.5V in our case, just the assumption we started with!

How does all this change, if the input voltage is not at virtual ground? To investigate this, assume Vin > 2.5V. In this case, we integrate faster down than up (keep in mind that the integrator is inverting). In this case, the output won't alternate each clock cycle, because we need more shallower up-integrating cycles to compensate the steeper slope of the down-integrating cycles. This in turn means that the output Q of U3A is more often low than high and the output /Q os more often high than low. The average of the bitstream is now higher than 0.5, which is totally in accordance with our assumption, Vin > Vref/2.

To make the long story short, the circuit figures out how many times (or how long) you have to add either -Vref/2 or +Vref/2 to your input voltage to get 0V, on average.

The given values in the schematic result in an input voltage range of -5V to +5V, of which only -4V to 4V should be used, because the more the input voltage approaches the limits, the less frequently the output bit value changes. In the extreme case (+5V or -5V) you end up with only ones or zeros at the output, but the software which processes the bitstream needs 0-to-1 and 1-to-0 transitions to detect the bit level voltages correctly.

D2 together with R205 provides some input protection.

Output signal level matching

The remaining task to do (and the remaining part of the schematic) is the level conversion from TTL logic levels (0V and 5V) to soundcard compatible levels. The R401/R402 and R404/R405 do the trick and the C40x achieve the desired AC coupling necessary for the soundcard.
R403/R406 prevent a loud click signal on the sound card input if the cable gets plugged in after power on.

Clock and and data can be fed seperately into the left and right channel or mixed together if GS1 is closed. The mixing function is needed for the SocDVM software and ony the mixed channel should be connected to either the right or left sound card input channel.

Some final words of caution: I built a single prototype of both circuits and their correct function was verified. This is not a design which was tried and tested extensively by numerous people
so your luck getting it to function may vary. Additionally there were some minor tweaks (like added protection diodes) to the schematics and layouts after the prototype was finished which were not tested in hardware, but should work fine.